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2017-09-06cpu: Fix bi-mode branch predictor thresholdsRico Amslinger
When different sizes were set for the choice and global saturation counter (e.g. ex5_big), the threshold calculation used the wrong size. Thus the branch predictor always predicted "not taken" for choice > global. Change-Id: I076549ff1482e2280cef24a0d16b7bb2122d4110 Reviewed-on: https://gem5-review.googlesource.com/4560 Reviewed-by: Curtis Dunham <curtis.dunham@arm.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2017-09-01cpu-minor: Fix for addr range coverage calculationPau Cabre
Coverage was wrongly set to PartialAddrRangeCoverage in the case of disjoint adjacent ranges Change-Id: I29aaf5145e6cdcf5f0b8f4e009d57ee57bd4c944 Signed-off-by: Pau Cabre <pau.cabre@metempsy.com> Reviewed-on: https://gem5-review.googlesource.com/4640 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2017-08-31scons: bump required python version to 2.7 to support pybind11Paul Rosenfeld
Change-Id: Ic3652f975477f2e5d144e054489ab73ed9f82b55 Reviewed-on: https://gem5-review.googlesource.com/4440 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Gabe Black <gabeblack@google.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Joe Gross <joe.gross@amd.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2017-08-30arch-arm: Only increment SW PMU counters on writes to PMSWINCJose Marinho
When writing a bitmask of counters to PMSWINC, the PMU currently increments the corresponding counters regardless of what they are configured to count. According to the ARM ARM (D5.10.4), counters should only be updated if they have been configured to count software events (event type 0). Change-Id: I5b2bc1fae55faa342b863721c9838342442831a9 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/4285 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2017-08-30arch-arm: Add missing override keywords in fault.hhAndreas Sandberg
Change-Id: I94a4bf4a633aeed550f8c01ccae824add3b85eb0 Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-on: https://gem5-review.googlesource.com/4284 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Curtis Dunham <curtis.dunham@arm.com>
2017-08-30arch-x86: Add missing override in the X86 TLBAndreas Sandberg
Change-Id: Ie5ef1aaaef46cf8ef8fa4b0fc8f7efb8cde9b489 Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-on: https://gem5-review.googlesource.com/4283 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2017-08-30arch-sparc: Add a FaultVals instantiation for VecDisabledAndreas Sandberg
Recent gcc versions complain about a missing VecDisabled not having an explicit FaultVals instantiation. Change-Id: I439e7b3a7d5cad20590f52b3f374ead3f3f070a6 Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-on: https://gem5-review.googlesource.com/4282 Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
2017-08-30arch-alpha: Add missing overridesAndreas Sandberg
Change-Id: I3a52fcdb449c7df1612466270aa2c9b0a0f3afef Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-on: https://gem5-review.googlesource.com/4281 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2017-08-30python: Make GlobalExitEvent.getCode() return an intAndreas Sandberg
PyBind normally casts integers returned from the C to long in Python. This is normally fine since long in most cases behaves just like an int. However, when passing the return value from getcode() to sys.exit, unexpected behavior ensues. Due to the way the function is defined, any type other than int (with the exception of None) will be treated as an error and be equivalent to sys.exit(1). Since we frequently use the sys.exit(event.getCode()) pattern, we need to ensure that the function returns an integer. This change adds an explicit type conversion to a Python integer in the wrapper code. Change-Id: I73d6b881025064afa2b2e6eb4512fa2a4b0a87da Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Jose Marinho <jose.marinho@arm.com> Reviewed-by: Curtis Dunham <curtis.dunham@arm.com> Reviewed-on: https://gem5-review.googlesource.com/4280 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Joe Gross <joe.gross@amd.com>
2017-08-30cpu-o3: fix data pkt initialization for split loadMatthias Hille
When a split load hits a memory region where IPRs are mapped, the Writebackevent which is scheduled for that was carrying a data packet that was not correctly initialized which caused an assertion to fire when the Writeback event is processed. Change-Id: I71a4e291f0086f7468d7e8124a0a8f098088972f Signed-off-by: Matthias Hille <matthiashille8@gmail.com> Reported-by: Matthias Hille <matthiashille8@gmail.com> Reviewed-on: https://gem5-review.googlesource.com/4620 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2017-08-28x86: Use the new CondInst format for moves to/from control registers.Gabe Black
The condition is whether the control register index is valid. Change-Id: I8a225fcfd4955032b5bbf7d3392ee5bcc7d6bc64 Reviewed-on: https://gem5-review.googlesource.com/4581 Reviewed-by: Michael LeBeane <Michael.Lebeane@amd.com> Maintainer: Gabe Black <gabeblack@google.com>
2017-08-28x86: Add a "CondInst" format for conditionally decoded instructions.Gabe Black
A condition can be specified which will tell the decoder whether to return the instruction being requested, or, if the condition fails, UD2. Change-Id: I0f1c075deb10754ce1dd88be1726a196294e41fd Reviewed-on: https://gem5-review.googlesource.com/4580 Reviewed-by: Michael LeBeane <Michael.Lebeane@amd.com> Maintainer: Gabe Black <gabeblack@google.com>
2017-08-12dev: Fix an IDE error check.Gabe Black
The error message says an IDE controller can support at most 4 disks, but the check would fail if there were more than 3 disks. Change-Id: Ic7d5d8c941fe2580da43019f53991377d4727bb9 Reviewed-on: https://gem5-review.googlesource.com/4460 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2017-08-08mem-cache: Delete squashed HWPrefetchesPau Cabre
Request and Packet for squashed HWPrefetches were not deleted Change-Id: I9b66bb01b8ed6a5ddfaaa8739a68165dc4a7006c Signed-off-by: Pau Cabre <pau.cabre@metempsy.com> Reviewed-on: https://gem5-review.googlesource.com/4340 Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
2017-08-03configs, arm: Fix incorrect use of mem_range in bL exampleAndreas Sandberg
The change "config: Change mem_range attribute naming in ARM SimpleSystem" modified the SimpleSystem class to be compatible with the MemConfig utility script. While doing so, the way we report the memory ranges supported by the system changed, which broke the bL example configration. This changeset introduces the necessary changes to make the script work again. Change-Id: I789987950ff04b6c5ae1c8b807355bcba34f6b3c Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/4380 Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
2017-08-03arm, config: Fix CPU names in ARM example configsAndreas Sandberg
The ARM example configs used to rely on CPU aliases for the AtomicSimpleCPU and KVM when configuring clusters. This broken when support for CPU aliases was removed ('config: Remove support for CPU aliases.'). This change updates the config scripts to use the full class names instead. Change-Id: If36c46207f39ca1897ecf77d9588f1c059819e63 Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-on: https://gem5-review.googlesource.com/4360 Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
2017-08-02base: Give more information when setting up asynchronous IO fails.Gabe Black
When asynchronous IO fails, gem5 currently just says it failed and quits, and doesn't give any more information about which step failed, or what specifically about it failed. This change adds two helpers which will attempt the fcntl, check for error conditions, and in the event of a failure, include a message describing the error code and what the arguments to fcntl were. Change-Id: I316478172ab2aefd3788279dbc12744791385cd5 Reviewed-on: https://gem5-review.googlesource.com/4320 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Gabe Black <gabeblack@google.com>
2017-08-01misc: git ignore file udpatedÉder F. Zulian
Change-Id: Ib2c7a7d26e7121dd082ca55a7c7ccf53fc47572c Reviewed-on: https://gem5-review.googlesource.com/4240 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2017-08-01style: Add shared gem5 headers to the style checkerAndreas Sandberg
Teach the style checker about common headers living in gem5/. These should be included after any global library headers (e.g., C headers or STL headers), but before the normal gem5 headers. Change-Id: I322f841420e361c16314be8fa4cbd1e86d2bfa9f Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/4300 Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
2017-08-01util: Move m5op.h to the shared include directoryAndreas Sandberg
The header file with C declarations for m5ops is sometimes needed by code outside of the util/m5 directory. Move this file to the shared include directory and factor out flags to a generic asm header. Note that applications that need to call m5ops still need to link with libm5.a or implement their own trampolines. Change-Id: I36a3f459ed71593e38b869dc2b1302c810f92276 Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Jose Marinho <jose.marinho@arm.com> Reviewed-on: https://gem5-review.googlesource.com/4265 Reviewed-by: Gabe Black <gabeblack@google.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
2017-08-01util, m5: Use consistent naming for m5op C symbolsAndreas Sandberg
Rename m5op C symbols to be prefixed all lower case, separated by underscore, and prefixed by m5. This avoids potential name clashes for short names such as arm. Change-Id: Ic42f94d8a722661ef96c151d627e31eeb2e51490 Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Jose Marinho <jose.marinho@arm.com> Reviewed-on: https://gem5-review.googlesource.com/4264 Reviewed-by: Gabe Black <gabeblack@google.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
2017-08-01arch-arm: Use named constants for m5op instructionsAndreas Sandberg
Change-Id: I544519c4f87e50cc02af29cbb3edc31ecf726e8e Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-on: https://gem5-review.googlesource.com/4263 Reviewed-by: Gabe Black <gabeblack@google.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
2017-08-01sim: Use named constants for pseudo opsAndreas Sandberg
Use named constants from a shared header instead of magic values when handling pseudo ops. Change-Id: If157060bbcd772ce7e8556482b44ca714f4319b1 Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-on: https://gem5-review.googlesource.com/4262 Reviewed-by: Gabe Black <gabeblack@google.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
2017-08-01util: Move the m5ops.h file to a shared directoryAndreas Sandberg
The header file m5ops.h contains a list of constants that should be shared between the simulator and utilities. Move this header file to a new top-level directory for shared files and rename constants to make them suitable for inclusion in the main simulator. The structure of the shared include directory is as follows: include/gem5: Files that can be included from C code. include/gem5/asm: Files that can be included from assembly code. asm/generic/: Files that aren't guest ISA specific asm/${isa}/: Files that are guest ISA specific Change-Id: I1aa511057bcaa80cc2d566109ff26581558c4a41 Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Jose Marinho <jose.marinho@arm.com> Reviewed-on: https://gem5-review.googlesource.com/4261 Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
2017-08-01kvm, arm: Switch to the device EQ when accessing ISA devicesAndreas Sandberg
ISA devices typically run in the device event queue. Previously, we assumed that devices would perform their own EQ migrations as needed. This isn't ideal since it means we have different conventions for IO devices and ISA devices. Switch to doing migrations in the KVM CPU instead to make the behavior consistent. Change-Id: I33b74480fb2126b0786dbdbfdcfa86083384250c Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-on: https://gem5-review.googlesource.com/4288 Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
2017-08-01kvm: Add a helper method to access device event queuesAndreas Sandberg
The VM's event queue is normally used for devices in multi-core KVM mode. Add a helper method, BaseKvmCPU::deviceEventQueue(), to access this queue. This makes the intention of code migrating to device event queues clearer. Change-Id: Ifb10f553a6d7445c8d562f658cf9d0b1f4c577ff Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-on: https://gem5-review.googlesource.com/4287 Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
2017-08-01cpu, kvm: Fix deadlock issue when resuming a drained systemAndreas Sandberg
The KVM CPU sometimes needs to access devices when drain() is called. This typically happens on ARM when synchronizing devices that use the system register interface. When called from drain(), the event queue isn't locked since drain is called from the outside when the simulator isn't servicing any events. In such cases, performing a migration to the device's queue will unlock a mutex that isn't locked. This typically results in a deadlock when resuming the system since the lock will be in an undefined state. Change-Id: Ibdcc2e034e916a929124f297e72aae306cf66728 Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: Curtis Dunham <curtis.dunham@arm.com> Reviewed-on: https://gem5-review.googlesource.com/4286 Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
2017-08-01arch-arm: Switch to DTOnly as the default machine typeAndreas Sandberg
Old ARM systems used to pass the machine type in the ATAGS list passed to the kernel. This has been largely deprecated by the introduction of device trees. Switch to the DTOnly machine type by default in gem5 since all new platforms and kernel will require this behavior. Change-Id: Icfd085e4862863b4ef495566bfddbd11591866c3 Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-on: https://gem5-review.googlesource.com/4260 Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
2017-07-28config: Discover CPU timing models based on target ISAAndreas Sandberg
The CpuConfig helper currently assumes that all timing models live in the cores.arm package. This ignores the potential mismatch between the target ISA and the ISA assumptions made by the timing models. Instead of unconditionally listing all CPU models in cores.arm, list timing models from cores.generic and cores.${TARGET_ISA}. This ensures that the listed timing models support the ISA that gem5 is targeting. Change-Id: If6235af2118889638f56ac4151003f38edfe9485 Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/3947 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2017-07-27config, arm: SE configuration for the ARM starter kitGabor Dozsa
Add a full system example configuration for the ARM Research Starter Kit on System Modeling. More information can be found at: http://www.arm.com/ResearchEnablement/SystemModeling Change-Id: Ia32a28eb713ba7050d790327ba6dbb73ec33b53a Signed-off-by: Gabor Dozsa <gabor.dozsa@arm.com> [ Minor cleanups and more documentation ] Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/4203 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2017-07-27config, arm: FS configuration for the ARM starter kitGabor Dozsa
Add a full system example configuration for the ARM Research Starter Kit on System Modeling. More information can be found at: http://www.arm.com/ResearchEnablement/SystemModeling Change-Id: Ifa40419d21923a32bb383d58466e421fe4260ddd Signed-off-by: Gabor Dozsa <gabor.dozsa@arm.com> [ Minor cleanups and more documentation ] Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/4202 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2017-07-27config, arm: Add a high-performance in order timing modelAshkan Tousi
The High-Performance In-order (HPI) CPU timing model is tuned to be representative of a modern in-order ARMv8-A implementation. The HPI core and its supporting simulation scripts, namely starter_se.py and starter_fs.py (under /configs/example/arm/) are part of the ARM Research Starter Kit on System Modeling. More information can be found at: http://www.arm.com/ResearchEnablement/SystemModeling Change-Id: I124bd06ba42d20abff09d447542b031d17eabe22 Signed-off-by: Ashkan Tousi <ashkan.tousimojarad@arm.com> Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/4201 Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
2017-07-27config: Change mem_range attribute naming in ARM SimpleSystemGabor Dozsa
MemConfig.config() expects memory ranges to be defined in a particular way. This patch changes the naming of the mem_range attribute in SympleSystem to enable use of MemConfig for configuring the memory. Change-Id: I4964c136e53a99c69ff5e086cacb929aa435168d Signed-off-by: Gabor Dozsa <gabor.dozsa@arm.com> Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/4200 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2017-07-25tests: Fix path for module imports in ARM system configsNikos Nikoleris
Change-Id: I6fd660da3899de1f8c61bf012532ff0437467302 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/4220 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2017-07-25configs,sim-se: fix se.py multi-cpu multi-cmd issuePau Cabre
Assign different pids to the different commands specified with the "--cmd" flag to configs/example/se.py Without this change, the following command line triggers a "fatal: _pid 100 is already used" error: command=$PWD/tests/test-progs/hello/bin/arm/linux/hello ./build/ARM/gem5.opt configs/example/se.py -n 2 -c "$command;$command" Change-Id: If6f726481eb196d4f42680b6aa46364fce4190ed Signed-off-by: Pau Cabre <pau.cabre@metempsy.com> Reviewed-on: https://gem5-review.googlesource.com/4160 Reviewed-by: Brandon Potter <Brandon.Potter@amd.com> Maintainer: Brandon Potter <Brandon.Potter@amd.com>
2017-07-20sim: Prevent segfault in the wakeCpu m5op if id is invalidJose Marinho
Change-Id: I86229cedb206e10326cdee3f09a5c871e49c8d48 Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/3965
2017-07-19cpu: Add missing rename of vector registers in the O3 CPURekai Gonzalez-Alberquilla
The introduction of a new vector register class broke rename in the O3 CPU due to an unhandled register class in DefaultRename<Impl>::renameSrcRegs(). This patch fixes adds the necessary handling to avoid a panic when the vector register file is used. Change-Id: Ie380ab35ec4a151db15402f25b25b58931ee0581 Reviewed-by: Giacomo Gabrielli <giacomo.gabrielli@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/4140 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2017-07-17cpu,o3: Fixed checkpointing bug occuring in the o3 CPUAnouk Van Laer
Checkpointing a system with out-of-order CPUs might get stuck if one of the CPUs has been put to sleep. The quiesce instruction cannot get drained hence checkpointing never finishes. This commit resolves that by activating all suspended thread contexts when draining the system. Change-Id: I817ab1672b4ead777bd8e12a0445829481c46fdc Reviewed-by: Sascha Bischoff <sascha.bischoff@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/3970 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2017-07-17tests: Don't treat new stats as a cause for failuresAndreas Sandberg
We currently fail the stat diff stage of tests if there are new stats. This is usually undesirable since this would require any change that adds a stat to also update the regressions. Change-Id: Ieadebac6fd17534e1b49b6b9a1d56f037a423325 Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-on: https://gem5-review.googlesource.com/3962 Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2017-07-17sim, x86: Make clone a virtual functionSean Wilson
This fixes the function call to clone in syscall_emul.hh where the x86 version should be called before the base implementation of clone. Change-Id: Iccd2f680ff6e3a5536037d688a80ab3f236bbd98 Signed-off-by: Sean Wilson <spwilson2@wisc.edu> Reviewed-on: https://gem5-review.googlesource.com/3902 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2017-07-17x86: Add stats to X86 TLBSwapnil Haria
Change-Id: Iebf7d245de66eebc8d4c59e62e52adf6cf51e1e4 Signed-off-by: Sean Wilson <spwilson2@wisc.edu> Reviewed-on: https://gem5-review.googlesource.com/3980 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2017-07-17riscv: Define register index constants using literalsAlec Roelke
To make it clearer what the register indices are for the semantically meaningful registers defined by src/arch/riscv/registers.hh, the constants that were defined using other constants were changed to use the literal values of those constants. This also removes the need to use the M5_VAR_USED attribute. Change-Id: I7cccbe45d3d820deb5149a5925415735f6ae2e61 Reviewed-on: https://gem5-review.googlesource.com/4080 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Alec Roelke <ar4jc@virginia.edu>
2017-07-14riscv: Disambiguate between the C and C++ versions of isnan and isinf.Gabe Black
When both the C and C++ versions are visible, the compiler will complain that it doesn't know which one to use. By specifying the std namespace, it will know to use the C++ version. Change-Id: Ie1bbe1d95eadbad9644b4915c21f924d7d5c0b22 Reviewed-on: https://gem5-review.googlesource.com/4060 Reviewed-by: Alec Roelke <ar4jc@virginia.edu> Maintainer: Alec Roelke <ar4jc@virginia.edu>
2017-07-14tests: Upate RISC-V binaries and resultsAlec Roelke
This patch updates the binaries and results for hello and insttest regressions using the compressed extension. Change-Id: I3d8f2248f490521d3e0dc05c48735cab82b1b04e Reviewed-on: https://gem5-review.googlesource.com/4042 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2017-07-14riscv: Fix bugs with RISC-V decoder and detailed CPUsAlec Roelke
This patch fixes some bugs that were missed with the changes to the decoder that enabled compatibility with compressed instructions. In order to accommodate speculation with variable instruction widths, a few assertions in decoder had to be changed to returning faults as the specification describes should normally happen. The rest of these assertions will be changed in a later patch. [Remove commented-out debugging line and add clarifying comment to registerName in utility.hh.] Change-Id: I3f333008430d4a905cb59547a3513f5149b43b95 Reviewed-on: https://gem5-review.googlesource.com/4041 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Alec Roelke <ar4jc@virginia.edu>
2017-07-14riscv: Add unused attribute to some registers.hh constantsAlec Roelke
Three of the constants defined in arch/riscv/registers.hh (ReturnValueReg, SyscallNumReg, and SyscallPseudoReturnReg) may cause the compiler to warn that they are unused, which results in an error. This patch adds M5_VAR_USED attributes to them to stop this. Change-Id: Ie6389a55e8ffb3d003a47d02e76bdf9fb5219457 Reviewed-on: https://gem5-review.googlesource.com/4040 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Alec Roelke <ar4jc@virginia.edu>
2017-07-13arch-arm: fix ldm of pc interswitching branchGedare Bloom
The LDM instruction that loads to the PC causes a branch to the instruction. In ARMv5T+ the branch can interswitch Thumb and ARM modes. The interswitch is broken prior to this commit, with LDM to the PC ignoring the switch. Change-Id: I6aad073206743f3435c9923e3e2218bfe32c7e05 Reviewed-on: https://gem5-review.googlesource.com/3520 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
2017-07-12ruby: Refactor some Event subclasses to lambdasSean Wilson
Change-Id: I9f47a20a869553515a759d9a29c05f6ce4b42d64 Signed-off-by: Sean Wilson <spwilson2@wisc.edu> Reviewed-on: https://gem5-review.googlesource.com/3930 Maintainer: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
2017-07-12arm: Refactor some Event subclasses to lambdasSean Wilson
Change-Id: Ic59add8afee1d49633634272d9687a4b1558537e Signed-off-by: Sean Wilson <spwilson2@wisc.edu> Reviewed-on: https://gem5-review.googlesource.com/3929 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2017-07-12dev: Refactor some Event subclasses to lambdasSean Wilson
Change-Id: I965d31ff8ad1658b03a902bf4244d7d0977b0466 Signed-off-by: Sean Wilson <spwilson2@wisc.edu> Reviewed-on: https://gem5-review.googlesource.com/3928 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
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