Age | Commit message (Collapse) | Author |
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into zamp.eecs.umich.edu:/z/ktlim2/clean/newmem-busfix
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constants.hh and isa_traits.cc
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called from the class's constructor.
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deterministic.
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than sprintf which was breaking on 64 bit hosts.
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control register fields which won't work on a big endian host.
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specific DepTag constants.
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bin files, cleanup lockstep printing a bit
Since we don't have a platform yet, you need to comment out the default responder stuff in Bus.py to make it work.
SConstruct:
Add TARGET_ISA to the list of environment variables that end up in the build_env for python
configs/common/FSConfig.py:
add a simple SPARC system to being testing with, you'll need to change makeLinuxAlphaSystem to makeSparcSystem in fs.py for now
src/SConscript:
add a raw file object, at least until we get more info about how to compile openboot properly
src/arch/sparc/system.cc:
src/arch/sparc/system.hh:
add parameters for ROM files (OBP/Reset/Hypervisor), a ROM, load files into ROM
src/base/loader/object_file.cc:
src/base/loader/object_file.hh:
add option to try raw when nothing works
src/cpu/exetrace.cc:
cleanup lockstep printing a little bit
src/cpu/m5legion_interface.h:
change the instruction to be 32 bits because it is
src/mem/physical.cc:
fix assert that doesn't work if memory starts somewhere above 0
src/python/m5/objects/BaseCPU.py:
Add if statement to choose between sparc tlbs and alpha tlbs
src/python/m5/objects/System.py:
Add a sparc system that sets the rom addresses correctly
src/python/m5/params.py:
add the ability to add Addr() together
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extra : convert_revision : bbbd8a56134f2dda2728091f740e2f7119b0c4af
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into zamp.eecs.umich.edu:/z/ktlim2/clean/newmem-busfix
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extra : convert_revision : dafe2d4a032b277c219ea13faf20567c20c1f2f4
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the TimingCPU. Now the Atomic CPU works with caches.
configs/common/Simulation.py:
Atomic CPU now works properly with caches, so we don't have to do extra parsing to hook up caches only to the timing CPU.
However the O3CPU must always use caches, so a check for that must still exist.
Also change the switch_cpus to be placed at the system level, now that Steve changed how the IntrController gets its CPU.
configs/example/fs.py:
configs/example/se.py:
Atomic CPU now handles caches.
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extra : convert_revision : 534ded558ef96cafd76b4b5c5317bd8f4d05076e
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files so the directories can easily be deleted.
Remove the FullCPU from the ALL_CPU_LIST and only add it if
it exists.
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src/cpu/o3/cpu.cc:
Handle draining properly when CPU isn't actually being used.
src/cpu/simple/atomic.cc:
Be sure to set status properly when draining.
src/mem/bus.cc:
Fix for draining.
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extra : convert_revision : d9796e6693e974f022159029fc9743c49a970c8f
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into zeep.eecs.umich.edu:/home/gblack/m5/newmemmemops
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extra : convert_revision : 0ab912df014cf1511e960e4058bee3eea047f9f6
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into zeep.eecs.umich.edu:/home/gblack/m5/newmemmemops
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extra : convert_revision : dc165840841bdd88e40111b98d1be493441703f0
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into zed.eecs.umich.edu:/z/hsul/work/m5/newmem
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extra : convert_revision : 5f4b39beba9f672ba1741cb45f4c3cf853ce574b
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into zeep.pool:/z/saidi/work/m5.newmem
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extra : convert_revision : 643e28482e6739bd264a9c2d69c17279853aa0c5
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align the character arrays that are used by placement-new for classes lest we have an unaligned fault on SPARC/Solaris
src/SConscript:
DWARF2 symbol support seems to be broken on Solaris. Use stabs+
src/base/statistics.hh:
align the character arrays that are used by placement-new for classes lest we have an unaligned fault on SPARC/Solaris
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extra : convert_revision : bc875a4fdfb4553062d3278537bc32a5ab9b6cca
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configs/common/Simulation.py:
simplify maxtick code a little bit - instead of checking for -1, just set it at MaxTick.
src/python/m5/__init__.py:
make a new m5 param called MaxTick.
src/sim/host.hh:
fix the M5 def. of MaxTick
src/sim/main.cc:
Simplify the MaxTick/num_cycles parsing within main.cc
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src/python/m5/objects/BaseCPU.py:
These parameters should have been removed in an earlier push.
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extra : convert_revision : 781b39ca370361e9568b1af0be96ff5848b1f3f4
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into zamp.eecs.umich.edu:/z/ktlim2/clean/newmem-busfix
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extra : convert_revision : 29426cebe81ac077c1a83f50e914ff6955ce81d4
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tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini:
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.out:
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini:
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.out:
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini:
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.out:
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini:
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.out:
Update config.
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stderr:
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stderr:
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stderr:
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stderr:
Update ref.
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extra : convert_revision : ca4fe7ff5bf9fcd112b703b88a5196a312c594ab
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faults for ua2005, and commented out ones which are apparently dropped.
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into zeep.eecs.umich.edu:/home/gblack/m5/newmemmemops
src/arch/sparc/faults.hh:
Hand merged.
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Apparently, gdb expects to do single stepping on its own, so those functions panic for SPARC. acc still needs to be implemented.
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rename : src/kern/alpha/idle_event.cc => src/arch/alpha/idle_event.cc
rename : src/kern/alpha/idle_event.hh => src/arch/alpha/idle_event.hh
rename : src/kern/alpha/kernel_stats.cc => src/arch/alpha/kernel_stats.cc
rename : src/kern/alpha/kernel_stats.hh => src/arch/alpha/kernel_stats.hh
rename : src/kern/sparc/kernel_stats.hh => src/arch/sparc/kernel_stats.hh
rename : src/kern/base_kernel_stats.cc => src/kern/kernel_stats.cc
rename : src/kern/base_kernel_stats.hh => src/kern/kernel_stats.hh
extra : convert_revision : 42bd3e36b407edbd19b912c9218f4e5923a15966
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into zizzer.eecs.umich.edu:/.automount/wexford/x/gblack/m5/newmemmemops
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src/python/m5/main.py:
add option to operate in lockstep with legion
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src/mem/bus.cc:
Fix up draining to work properly.
src/mem/bus.hh:
Initialize drainEvent to NULL.
src/mem/cache/base_cache.cc:
src/mem/cache/base_cache.hh:
Add draining to the caches.
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extra : convert_revision : 3082220a75d50876f10909f9f99bec535889f818
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