Age | Commit message (Collapse) | Author |
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into zeep.pool:/z/saidi/work/m5.newmem
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extra : convert_revision : 7b8b791815d1fb51cc7ad085307a640b2ee51642
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extra : convert_revision : 1221bfafe7af48ab04f63391f78eaf49d16077b3
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extra : convert_revision : 4665ac7760c9b78a1d7699ceeb541b694211a947
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extra : convert_revision : 1eaabd13c72aa42c512a04d162a87491818bc621
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extra : convert_revision : f9c78e86b60c3085cd95b1b4e132205e0ef584dd
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into zower.eecs.umich.edu:/eecshome/m5/newmem
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extra : convert_revision : 7bea2cb13e2de527134d98d4ee21a55dc4a7d1ad
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into zeep.pool:/z/saidi/work/m5.newmem
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extra : convert_revision : e302dc4d7a20646bb0ea363127b2658a6d6e810c
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into pb15.local:/Users/ali/work/m5.newmem.head
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extra : convert_revision : b4db0b350c8a5b3452ede74e5b42eec8ed6685c3
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return correct traps for ua2005 fpops that aren't implemented in hw
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extra : convert_revision : 998fd43f77c5de7078bac1c6caab296b18c9366d
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into zeep.pool:/z/saidi/work/m5.newmem
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extra : convert_revision : f25fd4855a1eaaecb29e6ccc3cee22cf07e4108b
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make fp writes also chatty with the Sparc traceflag
src/arch/sparc/floatregfile.cc:
make fp writes also chatty with the Sparc traceflag
src/cpu/exetrace.cc:
fix comparing fp registers between legion and m5
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extra : convert_revision : f3703afae56249f137451262bc1b6919d465e714
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into zower.eecs.umich.edu:/eecshome/m5/newmem
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extra : convert_revision : 2398e48722dd71ddf270e93bd7b387078fb30e6b
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the other param code so that other functions can use it
as well.
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extra : convert_revision : a8becdeadc70af0b64bff5b0770788dfba6e1857
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extra : convert_revision : 2fa44718e381ff743fa1cf12f4db2221dca87e4c
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SConstruct:
src/SConscript:
Add flags for Intel CC while i'm at it
src/base/compiler.hh:
the _Pragma stuff needst to be called this way unless someone happens to have a cleaner way
src/base/cprintf_formats.hh:
add std:: where appropriate
src/base/statistics.hh:
use this->map since icc was getting confused about std::map vs the locally defined map
src/cpu/static_inst.hh:
Add some more dummy returns where needed
src/mem/packet.hh:
add more dummy returns where needed
src/sim/host.hh:
use limits to come up with max tick
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extra : convert_revision : 08e9f7898b29fb9d063136529afb9b6abceab60c
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into zower.eecs.umich.edu:/eecshome/m5/newmem
src/arch/sparc/isa/formats/mem/util.isa:
src/arch/sparc/isa_traits.hh:
src/arch/sparc/system.cc:
Hand Merge
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extra : convert_revision : d5e0c97caebb616493e2f642e915969d7028109c
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extra : convert_revision : a79f5ee225208338594e7c4ecf0a71fef941918c
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possible now becauase Ctrl_Base_DepTag gets added into control register numbers.
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extra : convert_revision : d6de3be277127547cd942769cd34a54a4ec8db32
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into zeep.pool:/z/saidi/work/m5.newmem
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extra : convert_revision : ca6e616e64d4528478c1505dc7ce111b8888d389
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extra : convert_revision : 4b570a33a951e9286b38873b2be3651ffaee8532
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into zeep.pool:/z/saidi/work/m5.newmem
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extra : convert_revision : 53ee81b099930d4d827db99e2d944ffb8645c706
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some fixes to fp instructions to use the single precision registers
if this is an fp op emit fp check code
add fpregs to m5legion struct
src/arch/sparc/floatregfile.cc:
Make Sparc traceflag even more chatty
src/arch/sparc/isa/base.isa:
add code to check if the fpu is enabled
src/arch/sparc/isa/decoder.isa:
some fixes to fp instructions to use the single precision registers
fix smul again
fix subc/subcc/subccc condition code setting
src/arch/sparc/isa/formats/basic.isa:
src/arch/sparc/isa/formats/mem/util.isa:
if this is an fp op emit fp check code
src/cpu/exetrace.cc:
check fp regs as well as int regs
src/cpu/m5legion_interface.h:
add fpregs to m5legion struct
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extra : convert_revision : e7d26d10fb8ce88f96e3a51f84b48c3b3ad2f232
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into zeep.pool:/z/saidi/work/m5.suncc
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extra : convert_revision : 1706f6218abec7eb575dcff3ad4aef83894f64ab
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into zeep.pool:/z/saidi/work/m5.suncc
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extra : convert_revision : 20f61a524a3b53fc0afcf53a24b5a1fe1d96f579
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pretty close to compiling w/ suns compiler
briefly:
add dummy return after panic()/fatal()
split out flags by compiler vendor
include cstring and cmath where appropriate
use std namespace for string ops
SConstruct:
Add code to detect compiler and choose cflags based on detected compiler
Fix zlib check to work with suncc
src/SConscript:
split out flags by compiler vendor
src/arch/sparc/isa/decoder.isa:
use correct namespace for sqrt
src/arch/sparc/isa/formats/basic.isa:
add dummy return around panic
src/arch/sparc/isa/formats/integerop.isa:
use correct namespace for stringops
src/arch/sparc/isa/includes.isa:
include cstring and cmath where appropriate
src/arch/sparc/isa_traits.hh:
remove dangling comma
src/arch/sparc/system.cc:
dummy return to make sun cc front end happy
src/arch/sparc/tlb.cc:
src/base/compression/lzss_compression.cc:
use std namespace for string ops
src/arch/sparc/utility.hh:
no reason to say something is unsigned unsigned int
src/base/compression/null_compression.hh:
dummy returns to for suncc front end
src/base/cprintf.hh:
use standard variadic argument syntax instead of gnuc specefic renaming
src/base/hashmap.hh:
don't need to define hash for suncc
src/base/hostinfo.cc:
need stdio.h for sprintf
src/base/loader/object_file.cc:
munmap is in std namespace not null
src/base/misc.hh:
use M5 generic noreturn macros
use standard variadic macro __VA_ARGS__
src/base/pollevent.cc:
we need file.h for file flags
src/base/random.cc:
mess with include files to make suncc happy
src/base/remote_gdb.cc:
malloc memory for function instead of having a non-constant in an array size
src/base/statistics.hh:
use std namespace for floor
src/base/stats/text.cc:
include math.h for rint (cmath won't work)
src/base/time.cc:
use suncc version of ctime_r
src/base/time.hh:
change macro to work with both gcc and suncc
src/base/timebuf.hh:
include cstring from memset and use std::
src/base/trace.hh:
change variadic macros to be normal format
src/cpu/SConscript:
add dummy returns where appropriate
src/cpu/activity.cc:
include cstring for memset
src/cpu/exetrace.hh:
include cstring fro memcpy
src/cpu/simple/base.hh:
add dummy return for panic
src/dev/baddev.cc:
src/dev/pciconfigall.cc:
src/dev/platform.cc:
src/dev/sparc/t1000.cc:
add dummy return where appropriate
src/dev/ide_atareg.h:
make define work for both gnuc and suncc
src/dev/io_device.hh:
add dummy returns where approirate
src/dev/pcidev.hh:
src/mem/cache/cache_impl.hh:
src/mem/cache/miss/blocking_buffer.cc:
src/mem/cache/tags/lru.hh:
src/mem/cache/tags/split.hh:
src/mem/cache/tags/split_lifo.hh:
src/mem/cache/tags/split_lru.hh:
src/mem/dram.cc:
src/mem/packet.cc:
src/mem/port.cc:
include cstring for string ops
src/dev/sparc/mm_disk.cc:
add dummy return where appropriate
include cstring for string ops
src/mem/cache/miss/blocking_buffer.hh:
src/mem/port.hh:
Add dummy return where appropriate
src/mem/cache/tags/iic.cc:
cast hastSets to double for log() call
src/mem/physical.cc:
cast pmemAddr to char* for munmap
src/sim/byteswap.hh:
make define work for suncc and gnuc
--HG--
extra : convert_revision : ef8a1f1064e43b6c39838a85c01aee4f795497bd
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not just MaxGL.
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extra : convert_revision : 6fd090f112611db1e72a1f129dff03687d52930a
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into zed.eecs.umich.edu:/z/hsul/work/sparc/x86.m5
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extra : convert_revision : 1b854ec7caa33d3009383754206b643494c4c42d
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extra : convert_revision : 58e960e5019f944c7ec5606e4b8c93ce42330719
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extra : convert_revision : 9398362237443dc659f423a342bd27c923e90aea
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into zeep.pool:/y/binkertn/research/m5/rtc
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extra : convert_revision : 65ddda89f38c5fa874722c20e5d82ed1bb4e12d9
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pass the tuple of python's struct_time and interpret that.
Fixes a problem where the local timezone leaked into the time
calculation. Also fix things so that the unix, python, and RTC
data sheets all get the right time. Provide both years since 1900
and BCD two digit year.
Put the date back at 1/1/2006 for now.
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extra : convert_revision : 473244572f468de2cb579a3dd7ae296a6f81f5d7
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Only allow writing/reading of 32 bits of Y
Only allow writing/reading 32 bits of pc when pstate.am
Put any loaded data on the first half of a micro-op in uReg0 so it can't
overwrite the register we are using for address calculation
only erase a entry from the lookup table if it's valid
Put in a temporary check to make sure that lookup table and tlb array stay in sync
if we are interrupted in the middle of a mico-op, reset the micropc/nexpc
so we start on the first part of it when we come back
src/arch/sparc/isa/decoder.isa:
fix smul and sdiv to sign extend, and handle overflow/underflow corretly
Only allow writing/reading of 32 bits of Y
Only allow writing/reading 32 bits of pc when pstate.am
Put any loaded data on the first half of a micro-op in uReg0 so it can't
overwrite the register we are using for address calculation
src/arch/sparc/isa/formats/mem/blockmem.isa:
Put any loaded data on the first half of a micro-op in uReg0 so it can't
overwrite the register we are using for address calculation
src/arch/sparc/isa/includes.isa:
Use limits for 32bit underflow/overflow detection
src/arch/sparc/tlb.cc:
only erase a entry from the lookup table if it's valid
Put in a temporary check to make sure that lookup table and tlb array stay in sync
src/arch/sparc/tlb_map.hh:
add a print function to dump the tlb lookup table
src/cpu/simple/base.cc:
if we are interrupted in the middle of a mico-op, reset the micropc/nexpc
so we start on the first part of it when we come back
--HG--
extra : convert_revision : 50a23837fd888393a5c2aa35cbd1abeebb7f55d4
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--HG--
extra : convert_revision : 007e83ab452849ce527fe252148e7a1dc423c850
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into zower.eecs.umich.edu:/eecshome/m5/newmem
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extra : convert_revision : 2d7ae62a59b91d735bbac093f8a4ab542ea75eee
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check writability of tlb cache entry before using
update tagaccess in places I forgot to
move the tlb privileged test up since it is higher priority
src/arch/sparc/faults.cc:
save only 32 bits of PC/NPC if Pstate.am is set
src/arch/sparc/isa/decoder.isa:
return only 32 bits of PC/NPC if Pstate.am is set
increment cleanwin correctly
src/arch/sparc/tlb.cc:
check writability of cache entry
update tagaccess in a few more places
move the privileged test up since it is higher priority
src/cpu/exetrace.cc:
mask off upper bits of pc if pstate.am is set before comparing to legion
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extra : convert_revision : 02a51c141ee3f9a2600c28eac018ea7216f3655c
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--HG--
extra : convert_revision : bfb7db6bd118b623f6a38c05a962dc44456160cb
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extra : convert_revision : f9be59e94311571d91b6793b1caa1b6136ef864c
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into ewok.(none):/home/gblack/m5/newmemo3
src/sim/byteswap.hh:
Hand Merge
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extra : convert_revision : 640d33ad0c416934e8a5107768e7f1dce6709ca8
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extra : convert_revision : 1b5c1470ffc52b2f7719e469153702dec694f9a3
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extra : convert_revision : f7d21fc277dd7172c244d83fb012883dc8b67895
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simplify and make complete some asi checks
implement all the twin asis and remove panic checks on their use
soft int is supported, so we don't need to print writes to it
src/arch/sparc/asi.cc:
make AsiIsLittle() be all the little asis.
Speed up AsiIsTwin() a bit
src/arch/sparc/faults.cc:
clean up the do*Fault code.... Make it work like legion, in particular
pstate.priv is left alone, not set to 0 like the spec says
src/arch/sparc/isa/decoder.isa:
implement some more twin ASIs
src/arch/sparc/tlb.cc:
All the twin asis are implemented, no need to say their not supported anymore
src/arch/sparc/ua2005.cc:
softint is supported now, no more need to
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extra : convert_revision : aef2a1b93719235edff830a17a8ec52f23ec9f8b
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--HG--
extra : convert_revision : 4f5c7f9c7653e1e9ebbd488c07426d9f944bb25f
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into zeep.pool:/z/saidi/work/m5.newmem
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extra : convert_revision : 21e1bfa49a933f3b39bd2e7bcd873428f9d01a1b
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Only implemented for ELf. Someone might want to implement it for ecoff and some point
src/base/loader/elf_object.cc:
src/base/loader/elf_object.hh:
src/base/loader/object_file.cc:
src/base/loader/object_file.hh:
add a function to check if an executable is dynamic
src/sim/process.cc:
check if an executable is dynamic and die if it is
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extra : convert_revision : 830b1b50b08a5abaf895ce6251bbc702c986eebf
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Fix extracting of secondary context to shove into tag access register
properly sign extend va from 59 bits to 63 (SPARC VA hole)
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extra : convert_revision : 5d0c2b4db63338c31b2d29b4bb68f39e1d4f4c7b
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extra : convert_revision : f04af884687e9b8631e910cf62cd4a58d035c744
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extra : convert_revision : 52e51ff49f7ed73065f04707ded06dc7254292c4
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(the bit positition that is set in softint)
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extra : convert_revision : ba0e1f4ec1f74aac64c3f9bb7eb1b771e17b013a
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extra : convert_revision : 77bfdf07a49d41a2392f429fdc632c1461ac504c
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extra : convert_revision : 136b2bddc7cb70cde30e930ad3a13bd56c7162e1
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