Age | Commit message (Collapse) | Author |
|
into zeep.pool:/z/saidi/work/m5.newmem.head
--HG--
extra : convert_revision : c0f9bde20585b3811ff906728b003072b69696b5
|
|
--HG--
extra : convert_revision : 7a5fccb9a19d363e479ef24012a7b8598272eaa9
|
|
--HG--
extra : convert_revision : d9eb83ab77ffd2d725961f295b1733137e187711
|
|
and call it packet_access.hh and fix the #includes so
things compile right.
--HG--
extra : convert_revision : d3626c9715b9f7e51bb3ab8d97e971fad4e0b724
|
|
--HG--
extra : convert_revision : e1c107f0c0fd5d535acd2d6c43571a5df57c9ed3
|
|
--HG--
extra : convert_revision : a8a37c318e55e48e697e4aaba339328f000b3f60
|
|
--HG--
extra : convert_revision : 11bd043bb72eef0239fa60155e1f5a5e02de7cbc
|
|
util/term/term.c:
Reindent.
util/term/term.c:
Assume localhost if only port number is given on command line.
--HG--
extra : convert_revision : 768e61a56339a0795ca258cca788e9a2c20cbaae
|
|
I need to move over to using the fixPacket function so I don't have to make the same changes everywhere.
Still a functional access bug someplace I need to track down in timing mode.
src/mem/cache/base_cache.cc:
src/mem/cache/cache_impl.hh:
Fix corner case on assertion
tests/configs/memtest.py:
Updated memtester with uncacheable addresses and functional accesses
--HG--
extra : convert_revision : e6fa851621700ff9227b83cc5cac20af4fc8444f
|
|
that we could test it.
src/cpu/memtest/memtest.cc:
Fix memtest to do functional accesses
src/mem/cache/cache_impl.hh:
Fix cache to handle functional accesses properly based on memtester changes
Still need to fix functional accesses in timing mode now that the memtester can test it.
--HG--
extra : convert_revision : a6dbca4dc23763ca13560fbf5d41a23ddf021113
|
|
?? doesn't compile in warn statements
Should have been false, where I had a true.
src/cpu/o3/lsq_impl.hh:
Apparently you can't have ?? in a warn statement (Something about trigraphs)
src/mem/cache/cache_impl.hh:
Forgot to signal atomic mode in snoopProbe
--HG--
extra : convert_revision : c75cb76e193e852284564993440c8ea39e6de426
|
|
Now to try L2 caches in FS.
src/mem/cache/base_cache.hh:
Fix uni-coherence for atomic accesses in coherence protocol access to port
src/mem/cache/cache_impl.hh:
Properly handle uni-coherence
src/mem/cache/coherence/simple_coherence.hh:
Properly forward invalidates (not done for MSI+ protocols (assumed top level for now)
src/mem/cache/coherence/uni_coherence.cc:
src/mem/cache/coherence/uni_coherence.hh:
Properly forward invalidates in atomic/timing uni-coherence
--HG--
extra : convert_revision : f0f11315e8e7f32c19d92287f6f9c27b079c96f7
|
|
into zazzer.eecs.umich.edu:/z/rdreslin/m5bk/newmemcleanest
--HG--
extra : convert_revision : c6611b32537918f5bf183788227ddf69a9a9a069
|
|
src/mem/cache/cache_impl.hh:
Get the read data from the highest level of cache on a functional access
--HG--
extra : convert_revision : 7437ac46fb40f3ea3b42197a1aa8aec62af60181
|
|
--HG--
extra : convert_revision : 2c38c209d2f5cb0ee2f8e55fce6ee4400529d547
|
|
Mark as satisfied for functional snoops.
--HG--
extra : convert_revision : f75309c3436044a64caff097e2a585363cd004c3
|
|
into zizzer.eecs.umich.edu:/z/stever/bk/newmem-head
--HG--
extra : convert_revision : 8a70922250092c013fa4db6d83254b438ee6c4be
|
|
--HG--
extra : convert_revision : dcc699d8341f762dee659290cd35206e326e1179
|
|
that tracing gets turned on as the very first thing
in the selected cycle (tick).
--HG--
extra : convert_revision : c08f749ca42782af1b48e5aa5f0860bf7076bd3c
|
|
configs/example/fs.py:
Add MOESI protocol to caches (uni coherence not quite working w/FS yet).
--HG--
extra : convert_revision : 7bef7d9c5b24bf7241cc810df692408837b06b86
|
|
to convert to System ptr first to access System method.
src/python/m5/SimObject.py:
how did i not commit this already? the other way doesn't seem to work.
--HG--
extra : convert_revision : 55737d3d10742a1913a376d1febbc5809f2fab8f
|
|
--HG--
extra : convert_revision : e5e8b16ae4f119c923d8c0d295aa9569d7a8fe5b
|
|
--HG--
extra : convert_revision : 0cd0d31db44fe7e8e44bde90e1756873faca422f
|
|
--HG--
extra : convert_revision : ac4281944202a9a2f166b305a1eaea507e484bcc
|
|
into zazzer.eecs.umich.edu:/z/rdreslin/m5bk/newmemcleanest
--HG--
extra : convert_revision : 9e47881686a6c060fa28e7edfd9a0b556099bf30
|
|
Factor out some asserts that were on both
sides of an if/else.
--HG--
extra : convert_revision : 78f0c2d76a81a98216b2f281159c6b6ea0147731
|
|
Reindent due to resulting changes in nesting.
--HG--
extra : convert_revision : 6be099d572efb618efb08fbc06d7e0e4b5b4cab2
|
|
--HG--
extra : convert_revision : a701ed9d078c67718a33f4284c0403a8aaac7b25
|
|
--HG--
extra : convert_revision : 6aa97dcc807e175215e73c638faf73be926d4cd4
|
|
but not on zizzer... g++ 4 thing maybe?)
--HG--
extra : convert_revision : 31c49f1c55fe9daf6365411bfb5bb7f6ccc8032d
|
|
configs/example/fs.py:
Add flag for MP server systems.
src/python/m5/objects/AlphaConsole.py:
src/python/m5/objects/IntrControl.py:
Change CPU from 'any' to 'cpu[0]' to work better with MP sytems.
tests/configs/tsunami-simple-atomic-dual.py:
tests/configs/tsunami-simple-timing-dual.py:
Don't need to set console & intrcontrol cpu
params anymore (default is fixed now).
--HG--
extra : convert_revision : 9417b12b1b395ff7d6a9f2894e4123923c754daf
|
|
things and will test
src/mem/page_table.cc:
src/mem/page_table.hh:
add code to serialize/unserialize page table
src/sim/process.cc:
src/sim/process.hh:
add code to serialize/unserialize process
--HG--
extra : convert_revision : ee9eb5e2c38c5d317a2f381972c552d455e0db9e
|
|
Still a bug in atomic uni-coherence in FS.
src/cpu/o3/fetch_impl.hh:
src/cpu/o3/lsq_impl.hh:
src/cpu/simple/atomic.cc:
src/cpu/simple/timing.cc:
Make CPU models handle coherence requests
src/mem/cache/base_cache.cc:
Properly signal coherence CSHRs
src/mem/cache/coherence/uni_coherence.cc:
Only deallocate once
--HG--
extra : convert_revision : c4533de421c371c5532ee505e3ecd451511f5c99
|
|
after sending out a request.
Still need to rework upgrades into this system, but works for now.
src/mem/cache/base_cache.cc:
Re order code to be more readable
src/mem/cache/base_cache.hh:
Be sure to delete the copy on a bus block
src/mem/cache/cache_impl.hh:
Be sure to remove the copy on a writeback success
src/mem/cache/miss/mshr_queue.cc:
Demorgans to make it easier to understand
src/mem/tport.cc:
Delete writebacks
--HG--
extra : convert_revision : 9519fb37b46ead781d340de29bb342a322a6a92e
|
|
writebacks delete the packet.
--HG--
extra : convert_revision : 72b1c6296a16319f4d16c62bc7038365654dbc40
|
|
sendTiming.
Still need to fix upgrades to use this path
src/mem/cache/base_cache.cc:
Copy the pkt to the MSHR before issuing the sendTiming where it may be changed/consumed
src/mem/cache/cache_impl.hh:
Use copy of packet, because sendTiming may have changed the pkt
Also, delete the copy when the time comes
--HG--
extra : convert_revision : 635cde6b4f08d010affde310c46b1caf50fbe424
|
|
into zazzer.eecs.umich.edu:/z/rdreslin/m5bk/newmemcleanest
--HG--
extra : convert_revision : e33d535feb0c3d975dc043efdc86efe0df05800c
|
|
Clean up a little.
--HG--
extra : convert_revision : db5f36776209c76a593205c46b08aa147358f33a
|
|
into zazzer.eecs.umich.edu:/z/rdreslin/m5bk/newmemcleanest
--HG--
extra : convert_revision : c3650273684f3fbdcd2e14e95d09ee3c6de8d6b6
|
|
--HG--
extra : convert_revision : d5c0aadc35edf5c9495afcd3375f1f64716ef845
|
|
into zizzer.eecs.umich.edu:/.automount/wexford/x/gblack/m5/newmem_bus
--HG--
extra : convert_revision : ff15f3805a9ed9aa81e92013d5b57399a30720bb
|
|
--HG--
extra : convert_revision : c081754c8eb8fa5b8e7336deb3fefb545789b8ac
|
|
but I believe it should fix what she's running into (which was definitely a bug).
src/cpu/o3/fetch_impl.hh:
Move assertion to area where it should really always be true. Sometimes you might recvRetry and not necessarily be blocked (if there was a squash).
--HG--
extra : convert_revision : 76ad35357e7f4c44fa544ffed071096a62053018
|
|
into zazzer.eecs.umich.edu:/z/rdreslin/m5bk/newmemcleanest
--HG--
extra : convert_revision : f62790e46a7e3eb88a6f8c7bfaa08526285248a3
|
|
Fix CSHR's for flow control.
Fix for Bus Bridges reusing packets (clean flags up)
Now both timing/atomic caches with MOESI in UP fail at same point.
src/dev/io_device.hh:
DMA's should send WriteInvalidates
src/mem/bridge.cc:
Reusing packet, clean flags in the packet set by bus.
src/mem/cache/base_cache.cc:
src/mem/cache/base_cache.hh:
src/mem/cache/cache.hh:
src/mem/cache/cache_impl.hh:
src/mem/cache/coherence/simple_coherence.hh:
src/mem/cache/coherence/uni_coherence.cc:
src/mem/cache/coherence/uni_coherence.hh:
Fix CSHR's for flow control.
src/mem/packet.hh:
Make a writeInvalidateResp, since the DMA expects responses to it's writes
--HG--
extra : convert_revision : 59fd6658bcc0d076f4b143169caca946472a86cd
|
|
--HG--
extra : convert_revision : cd0d13a85ddc7599308db8604a8f63a48679cc05
|
|
into zed.eecs.umich.edu:/z/hsul/work/m5/newmem
src/cpu/simple/timing.cc:
hand merge
--HG--
extra : convert_revision : 083bf102249ad9bc63c447dbf85d3863f935f647
|
|
fixPacket() should be used anywhere a functional packet and timing packet are found to have the same address.
--HG--
extra : convert_revision : 783ec438271b24ddb0ae742b4efd1ed7d6be93f3
|
|
into zooks.eecs.umich.edu:/y/ksewell/research/m5-sim/cleanrepo
--HG--
extra : convert_revision : f02fd56fc1ec658fe2a81d0e0b0d053b7606f7f2
|
|
--HG--
extra : convert_revision : b873e0b436d71d86b87b8d9df7115bcc7ceb2b50
|