Age | Commit message (Collapse) | Author | |
---|---|---|---|
2010-07-22 | Power: Provide a utility function to copy registers from one thread context | Timothy M. Jones | |
to another in the Power ISA. | |||
2010-07-21 | stats: unify the two stats distribution type better | Nathan Binkert | |
2010-07-21 | stats: cleanup a few small problems in stats | Nathan Binkert | |
2010-07-21 | python: add a sorted dictionary class | Nathan Binkert | |
It would be nice if python had a tree class that would do this for real, but since we don't, we'll just keep a sorted list of keys and update it on demand. | |||
2010-07-21 | python: Add mechanism to override code compiled into the exectuable | Nathan Binkert | |
If the user sets the environment variable M5_OVERRIDE_PY_SOURCE to True, then imports that would normally find python code compiled into the executable will instead first check in the absolute location where the code was found during the build of the executable. This only works for files in the src (or extras) directories, not automatically generated files. This is a developer feature! | |||
2010-07-21 | Fix x86 XCHG macro-op to use locked micro-ops for all memory accesses | Tushar Krishna | |
2010-07-17 | SimObject: transparently forward Python attribute refs to C++. | Steve Reinhardt | |
This tidbit was pulled from a larger patch for Tim's sake, so the comment reflects functions that haven't been exported yet. I hope to commit them soon so it didn't seem worth cleaning up. | |||
2010-07-15 | ARM: Make an SRS instruction with a bad mode cause an undefined instruction ↵ | Gabe Black | |
fault. | |||
2010-07-13 | ARM: Adjust the FP_Base_DepTag to be larger than the largest int reg index. | Gabe Black | |
2010-07-08 | cache: fix bug in SC upgrade handling | Steve Reinhardt | |
This bug was introduced with the recent rework of SC failure handling in cset f97b62be544f. | |||
2010-07-08 | garnet: Added topology print function to Garnet printStats | Brad Beckmann | |
2010-07-08 | NetworkMessage copy constructor fix | Tushar Krishna | |
2010-07-05 | checkpointing: another small overload fix | Steve Reinhardt | |
On Nate's advice, overload 'char' as well as 'signed char' and 'unsigned char'. | |||
2010-07-05 | sim: allow SimObject subclasses to define classmethods | Steve Reinhardt | |
(without requiring a leading underscore) Also a little cleanup on type names in SimObject.py. | |||
2010-07-05 | sim: fold StartupCallback into SimObject | Steve Reinhardt | |
There used to be a reason to have StartupCallback be a separate object, but not any more. Now it's just confusing. | |||
2010-07-05 | checkpointing: minor cleanup. | Steve Reinhardt | |
Move some static checkpoint stuff into the Checkpoint object namespace. | |||
2010-07-05 | checkpointing: fix minor bug | Steve Reinhardt | |
Somehow we now need to explicitly specialize on 'signed char' and not just 'char' to catch cases like int8_t | |||
2010-07-05 | util: add a script for testing checkpointing | Steve Reinhardt | |
See comments in util/checkpoint-tester.py for details. | |||
2010-07-05 | process: get rid of some unused code & vars | Steve Reinhardt | |
2010-07-05 | process: minor format/style cleanup | Steve Reinhardt | |
2010-06-22 | style: updated garnet to match M5 coding style | Tushar Krishna | |
2010-06-28 | inorder: remove another debug stat | Korey Sewell | |
2010-06-26 | inorder: remove debugging stat | Korey Sewell | |
m5 doesnt do stats specific to binary and this resource request stat is probably only useful for people who really know the ins/outs of the model anyway | |||
2010-06-25 | inorder: update regressions from RAS fix | Korey Sewell | |
2010-06-25 | inorder: Return Address Stack bug | Korey Sewell | |
the nextPC was getting sent to the branch predictor not the current PC, so the RAS was returning the wrong PC and mispredicting everything. | |||
2010-06-25 | inorder: resource scheduling backend | Korey Sewell | |
replace priority queue with vector of lists(1 list per stage) and place inside a class so that we have more control of when an instruction uses a particular schedule entry ... also, this is the 1st step toward making the InOrderCPU fully parameterizable. See the wiki for details on this process | |||
2010-06-25 | X86: Fix div2 flag calculation. | Gabe Black | |
2010-06-24 | inorder: update regressions | Korey Sewell | |
2010-06-24 | inorder: cleanup virtual functions | Korey Sewell | |
remove the annotation 'virtual' from function declaration that isnt being derived from | |||
2010-06-24 | inorder: enforce 78-character rule | Korey Sewell | |
2010-06-24 | inorder: exe_unit_stats for resolved branches | Korey Sewell | |
2010-06-23 | inorder: squash from memory stall | Korey Sewell | |
this applies to multithreading models which would like to squash a thread on memory stall | |||
2010-06-23 | inorder: update regressions | Korey Sewell | |
2010-06-23 | inorder: record load/store trace data | Korey Sewell | |
2010-06-23 | inorder: update branch predictor | Korey Sewell | |
- use InOrderBPred instead of Resource for DPRINTFs - account for DELAY SLOT in updating RAS and in squashing - don't let squashed instructions update the predictor - the BTB needs to use the ASID not the TID to work for multithreaded programs - add stats for BTB hits | |||
2010-06-23 | inorder-stats: add instruction type stats | Korey Sewell | |
also, remove inst-req stats as default.good for debugging but in terms of pure processor stats they aren't useful | |||
2010-06-23 | inorder: stall signal handling | Korey Sewell | |
remove stall only when necessary add debugging printfs | |||
2010-06-23 | inorder: tick scheduling | Korey Sewell | |
use nextCycle to calculate ticks after addition | |||
2010-06-22 | cache: fix longstanding prefetcher bug | Steve Reinhardt | |
Thanks to Joe Gross for pointing this out (again?). Apologies to anyone who pointed it out earlier and we didn't listen. | |||
2010-06-23 | O3ThreadContext: When taking over from a previous context, only assert that | Timothy M. Jones | |
the system pointers match in Full System mode. | |||
2010-06-16 | stats: update stats for SC protocol change | Steve Reinhardt | |
Some subset of UpgradeReq messages shifted to the new SCUpgradeReq type. Other than that there are no significant differences. | |||
2010-06-16 | cache: fail store conditionals when upgrade loses race | Steve Reinhardt | |
Requires new "SCUpgradeReq" message that marks upgrades for store conditionals, so downstream caches can fail these when they run into invalidations. See http://www.m5sim.org/flyspray/task/197 | |||
2010-06-16 | cache: fix dirty bit setting | Steve Reinhardt | |
Only set the dirty bit when we actually write to a block (not if we thought we might but didn't, as in a failed SC or CAS). This requires makeing sure the dirty bit stays set when we get an exclusive (writable) copy in a cache-to-cache transfer from another owner, which n turn requires copying the mem-inhibit flag from timing-mode requests to their associated responses. | |||
2010-06-15 | stats: rename print to display in the mysql code too...sorry | Nathan Binkert | |
2010-06-15 | stats: rename print to display so it work in python | Nathan Binkert | |
2010-06-15 | stats: only consider a formula initialized if there is a formula | Nathan Binkert | |
2010-06-14 | stats: get rid of the never-really-used event stuff | Nathan Binkert | |
2010-06-14 | util: clean up attrdict and import multiattrdict into m5.util | Nathan Binkert | |
2010-06-14 | python: use ipython in --interactive if it is available | Nathan Binkert | |
2010-06-14 | build: grab the right library if we're using a debug version of python | Nathan Binkert | |