gem5 - gem5

Age	Commit message (Collapse)	Author
2013-11-29	base: Clean up signal handling	Andreas Sandberg
	The PollEvent class dynamically installs a SIGIO and SIGALRM handler when a file handler is registered. Most signal handlers currently get registered in the initSignals() function. This changeset moves the SIGIO/SIGALRM handlers to initSignals() to live with the other signal handlers. The original code installs SIGIO and SIGALRM with the SA_RESTART option to prevent syscalls from returning EINTR. This changeset consistently uses this flag for all signal handlers to ensure that other signals that trigger asynchronous behavior (e.g., statistics dumping) do not cause undesirable EINTR returns.
2013-11-26	stats: updates due to changes to ticksToCycles()	Nilay Vaish

2013-11-26	sim: correct ticksToCycles() function.	Nilay Vaish

2013-10-15	kvm: Set the perf exclude_host attribute if available	Andreas Sandberg
	The performance counting framework in Linux 3.2 and onwards supports an attribute to exclude events generated by the host when running KVM. Setting this attribute allows us to get more reliable measurements of the guest machine. For example, on a highly loaded system, the instruction counts from the guest can be severely distorted by the host kernel (e.g., by page fault handlers). This changeset introduces a check for the attribute and enables it in the KVM CPU if present.
2013-11-26	x86: Implementation of Int3 and Int_Ib in long mode	Christian Menard
	This is an implementation of the x86 int3 and int immediate instructions for long mode according to 'AMD64 Programmers Manual Volume 3'.
2013-11-26	kvm: Remove the unused hostFreq member from BaseKvmCPU	Andreas Sandberg

2013-11-25	sim: simulate with multiple threads and event queues	Steve Reinhardt ext:(%2C%20Nilay%20Vaish%20%3Cnilay%40cs.wisc.edu%3E%2C%20Ali%20Saidi%20%3CAli.Saidi%40ARM.com%3E)
	This patch adds support for simulating with multiple threads, each of which operates on an event queue. Each sim object specifies which eventq is would like to be on. A custom barrier implementation is being added using which eventqs synchronize. The patch was tested in two different configurations: 1. ruby_network_test.py: in this simulation L1 cache controllers receive requests from the cpu. The requests are replied to immediately without any communication taking place with any other level. 2. twosys-tsunami-simple-atomic: this configuration simulates a client-server system which are connected by an ethernet link. We still lack the ability to communicate using message buffers or ports. But other things like simulation start and end, synchronizing after every quantum are working. Committed by: Nilay Vaish
2013-11-15	cpu: allow the fetch buffer to be smaller than a cache line	Anthony Gutierrez
	the current implementation of the fetch buffer in the o3 cpu is only allowed to be the size of a cache line. some architectures, e.g., ARM, have fetch buffers smaller than a cache line, see slide 22 at: http://www.arm.com/files/pdf/at-exploring_the_design_of_the_cortex-a15.pdf this patch allows the fetch buffer to be set to values smaller than a cache line.
2013-11-15	cpu: Fix Checker register index use	Andreas Hansson
	This patch fixes an issue in the checker CPU register indexing. The code will not even compile using LTO as deep inlining causes the used index to be outside the array bounds.
2013-11-14	tests: suppress output on switcheroo tests	Steve Reinhardt
	The output from the switcheroo tests is voluminous and (because it includes timestamps) highly sensitive to minor changes, leading to extremely large updates to the reference outputs. This patch addresses this problem by suppressing output from the tests. An internal parameter can be set to enable the output. Wiring that up to a command-line flag (perhaps even the rudimantary -v/-q options in m5/main.py) is left for future work.
2013-11-12	sim: fix event priority name for debug-start option	Anthony Gutierrez

2013-11-01	stats: Bump stats to match DRAM controller changes	Andreas Hansson
	This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01	mem: Fixes for DRAM stats accounting	Andreas Hansson
	This patch fixes a number of stats accounting issues in the DRAM controller. Most importantly, it separates the system interface and DRAM interface so that it is clearer what the actual DRAM bandwidth (and consequently utilisation) is.
2013-11-01	mem: Fix the LPDDR3 page size	Andreas Hansson
	This patch corrects the LPDDR3 page size, which was set too low.
2013-11-01	mem: Adding stats for DRAM power calculation	Neha Agarwal
	This patch adds stats which are used for offline power calculation from the 'Micron Power Calculator' spreadsheet.
2013-11-01	mem: Unify request selection for read and write queues	Neha Agarwal
	This patch unifies the request selection across read and write queues for FR-FCFS scheduling policy. It also fixes the request selection code to prioritize the row hits present in the request queues over the selection based on earliest bank availability.
2013-11-01	mem: Add a simple adaptive version of the open-page policy	Andreas Hansson
	This patch adds a basic adaptive version of the open-page policy that guides the decision to keep open or close by looking at the contents of the controller queues. If no row hits are found, and bank conflicts are present, then the row is closed by means of an auto precharge. This is a well-known technique that should improve performance in most use-cases.
2013-11-01	mem: Just-in-time write scheduling in DRAM controller	Neha Agarwal
	This patch removes the untimed while loop in the write scheduling mechanism and now schedule commands taking into account the minimum timing constraint. It also introduces an optimization to track write queue size and switch from writes to reads if the number of write requests fall below write low threshold.
2013-11-01	mem: Add tRRD as a timing parameter for the DRAM controller	Andreas Hansson
	This patch adds the tRRD parameter to the DRAM controller. With the recent addition of the actAllowedAt member for each bank, this addition is trivial.
2013-11-01	mem: Less conservative tRAS in DRAM configurations	Andreas Hansson
	This patch changes the default values of the tRAS timing parameter to be less conservative, and closer in line with existing parts.
2013-11-01	mem: Make tXAW enforcement less conservative and per rank	Ani Udipi
	This patch changes the tXAW constraint so that it is enforced per rank rather than globally for all ranks in the channel. It also avoids using the bank freeAt to enforce the activation limit, as doing so also precludes performing any column or row command to the DRAM. Instead the patch introduces a new variable actAllowedAt for the banks and use this to track when a potential activation can occur.
2013-11-01	mem: Fix for 100% write threshold in DRAM controller	Neha Agarwal
	This patch fixes the controller when a write threshold of 100% is used. Earlier for 100% write threshold no data is written to memory as writes never get triggered since this corner case is not considered.
2013-11-01	mem: Pick the next DRAM request based on bank availability	Andreas Hansson
	This patch changes the FCFS bit of FR-FCFS such that requests that target the earliest available bank are picked first (as suggested in the original work on FR-FCFS by Rixner et al). To accommodate this we add functionality to identify a bank through a one-dimensional identifier (bank id). The member names of the DRAMPacket are also update to match the style guide.
2013-11-01	mem: Use the same timing calculation for DRAM read and write	Ani Udipi
	This patch simplifies the DRAM model by re-using the function that computes the busy and access time for both reads and writes.
2013-11-01	mem: Fix DRAM bank occupancy for streaming access	Ani Udipi
	This patch fixes an issue that allowed more than 100% bus utilisation in certain cases.
2013-11-01	mem: Schedule time for DRAM event taking tRAS into account	Ani Udipi
	This patch changes the time the controller is woken up to take the next scheduling decisions. tRAS is now handled in estimateLatency and doDRAMAccess and we do not need to worry about it at scheduling time. The earliest we need to wake up is to do a pre-charge, row access and column access before the bus becomes free for use.
2013-11-01	mem: Add tRAS parameter to the DRAM controller model	Ani Udipi
	This patch adds an explicit tRAS parameter to the DRAM controller model. Previously tRAS was, rather conservatively, assumed to be tRCD + tCL + tRP. The default values for tRAS are chosen to match the previous behaviour and will be updated later.
2013-11-01	stats: Bump stats after shifting to SimpleMemory	Andreas Hansson
	Match stats with new regression configs.
2013-11-01	test: Use SimpleMemory for atomic full-system tests	Andreas Hansson
	Keep it simple and use the SimpleMemory rather than the DRAM controller model for atomic full-system tests.
2013-11-01	sim: Clarify the difference between tracing and debugging	Andreas Hansson
	This patch changes the name the command-line options related to debug output to all start with "debug" rather than being a mix of that and "trace". It also makes it clear that the breakpoint time is specified in ticks and not in cycles.
2013-10-31	ARM: add support for TEEHBR access	Chander Sudanthi
	Thumb2 ARM kernels may access the TEEHBR via thumbee_notifier in arch/arm/kernel/thumbee.c. The Linux kernel code just seems to be saving and restoring the register. This patch adds support for the TEEHBR cp14 register. Note, this may be a special case when restoring from an image that was run on a system that supports ThumbEE.
2013-10-31	dev: Add 'OSC' oscillator sys control reg support to VersatileExpress	Matt Evans
	The VE motherboard provides a set of system control registers through which various motherboard and coretile registers are accessed. Voltage regulators and oscillator (DLL/PLL) config are examples. These registers must be impleted to boot Linux 3.9+ kernels.
2013-10-31	dev: Add support for MSI-X and Capability Lists for ARM and PCI devices	Geoffrey Blake
	This patch adds the registers and fields to the PCI device to support Capability lists and to support MSI-X in the GIC.
2013-10-31	dev: Fix race conditions in IDE device on newer kernels	Geoffrey Blake
	Newer linux kernels and distros exercise more functionality in the IDE device than previously, exposing 2 races. The first race is the handling of aborted DMA commands would immediately report the device is ready back to the kernel and cause already in flight commands to assert the simulator when they returned and discovered an inconsitent device state. The second race was due to the Status register not being handled correctly, the interrupt status bit would get stuck at 1 and the driver eventually views this as a bad state and logs the condition to the terminal. This patch fixes these two conditions by making the device handle aborted commands gracefully and properly handles clearing the interrupt status bit in the Status register.
2013-10-31	base: Add support for ipv6 into inet.hh/inet.cc	Geoffrey Blake

2013-10-31	cpu: Construct ROB with cpu params struct instead of each variable	Faissal Sleiman
	Most other structures/stages get passed the cpu params struct.
2013-10-31	config: Fix handling of parents for simobject vectors	Geoffrey Blake
	SimObjectVector objects did not provide the same interface to the _parent attribute through get_parent() like a normal SimObject. It also handled assigning a _parent incorrectly if objects in a SimObjectVector were changed post-creation, leading to errors later when the simulator tried to execute. This patch fixes these two omissions.
2013-10-31	sim: added option to serialize SimLoopExitEvent	Dam Sunwoo
	SimLoopExitEvents weren't serialized by default. Some benchmarks utilize a delayed m5 exit pseudo op call to terminate the simulation and this event was lost when resuming from a checkpoint generated after the pseudo op call. This patch adds the capability to serialize the SimLoopExitEvents and enable serialization for m5_exit and m5_fail pseudo ops by default. Does not affect other generic SimLoopExitEvents.
2013-10-31	mem: Add "const" attribute to Packet getters	Stephan Diestelhorst
	Add a "const" keywords to the getters in the Packet class so these can be invoked on const Packet objects.
2013-10-31	mem: Add privilege info to request class	Prakash Ramrakhyani
	This patch adds a flag in the request class that indicates if the request was made in privileged mode.
2013-10-31	arm: fix m5ops binary for ARM and add m5fail.	Ali Saidi
	Changes to make m5ops work under virtualization seemed to break them working with non-virtualized systems and the recently added m5 fail command makes the m5op binary not compile. For now remove the code for virtualization.
2013-10-31	cpu: Fix O3 issuse with load+barrier instructions.	Ali Saidi
	Fix a problem in the O3 CPU for instructions that are both memory loads and memory barriers (e.g. load acquire) and to uncacheable memory. This combination can confuse the commit stage into commitng an instruction that hasn't executed and got it's value yet. At the same time refactor the code slightly to remove duplication between two of the cases.
2013-10-30	ruby: set SenderMachine in messages of MOESI_CMP_directory	Lluc Alvarez
	This patch adds missing initializations of the SenderMachine field of out_msg's when thery are created in the L2 cache controller of the MOESI_CMP_directory coherence protocol. When an out_msg is created and this field is left uninitialized, it is set to the default value MachineType_NUM. This causes a panic in the MachineType_to_string function when gem5 is executed with the Ruby debug flag on and it tries to print the message. Committed by: Nilay Vaish <nilay@cs.wisc.edu>
2013-10-30	ruby: Fixed a deadlock when restoring a checkpoint with garnet	Emilio Castillo
	This patch fixes a problem where in Garnet, the enqueue time in the VCallocator and the SWallocator which is of type Cycles was being stored inside a variable with int type. This lead to a known problem restoring checkpoints with garnet & the fixed pipeline enabled. That value was really big and didn't fit in the variable overflowing it, therefore some conditions on the VC allocation stage & the SW allocation stage were not met and the packets didn't advance through the network, leading to a deadlock panic right after the checkpoint was restored. Committed by: Nilay Vaish <nilay@cs.wisc.edu>
2013-10-17	mem: De-virtualise interfaces in the CoherentBus	Stephan Diestelhorst
	The CoherentBus eventually got virtual methods for its interface. The "virtuality" of the CoherentBus, however, comes already from the virtual interface of the bus' ports. There is no need to add another layer of virtual functions, here.
2013-10-17	cpu: add consistent guarding to *_impl.hh files.	Matt Horsnell

2013-10-17	mem: Add PortID to QueuedMasterPort constructor	Sascha Bischoff
	This patch adds the PortID to the QueuedMasterPort. This allows a PortID to be specified as it previously was set to the detault value of -1.
2013-10-17	arm: Add a 'clear PPI' method to gic_pl390	Matt Evans
	The underlying assumption that all PPIs must be edge-triggered is strained when the architected timers and VGIC interfaces make level-behaviour observable. For example, a virtual timer interrupt 'goes away' when the hypervisor is entered and the vtimer is disabled; this requires a PPI to be de-activated. The new method simply clears the interrupt pending state.
2013-10-17	config: Fix ommission of number base in ethernet address param	Geoffrey Blake
	The ethernet address param tries to convert a hexadecimal string using int() in python, which defaults to base 10, need to specify base 16 in this case.
2013-10-17	config: Fix for port references generated multiple times	Geoffrey Blake
	SimObjects are expected to only generate one port reference per port belonging to them. There is a subtle bug with using "not" here as a VectorPort is seen as not having a reference if it is either None or empty as per Python docs sec 9.9 for Standard operators. Intended behavior is to only check if we have not created the reference.