| Age | Commit message (Collapse) | Author | |
|---|---|---|---|
| 2009-06-05 | types: need typename keyword to get the type. | Nathan Binkert | |
| 2009-06-04 | types: clean up types, especially signed vs unsigned | Nathan Binkert | |
| 2009-06-04 | move: put predictor includes and cc files into the same place | Nathan Binkert | |
| --HG-- rename : src/cpu/2bit_local_pred.cc => src/cpu/pred/2bit_local.cc rename : src/cpu/o3/2bit_local_pred.hh => src/cpu/pred/2bit_local.hh rename : src/cpu/btb.cc => src/cpu/pred/btb.cc rename : src/cpu/o3/btb.hh => src/cpu/pred/btb.hh rename : src/cpu/ras.cc => src/cpu/pred/ras.cc rename : src/cpu/o3/ras.hh => src/cpu/pred/ras.hh rename : src/cpu/tournament_pred.cc => src/cpu/pred/tournament.cc rename : src/cpu/o3/tournament_pred.hh => src/cpu/pred/tournament.hh | |||
| 2009-06-04 | style: cleanup style | Nathan Binkert | |
| 2009-06-01 | swig: %include Event before PythonEvent so python gets the subclass correct. | Nathan Binkert | |
| Before this change, some versions of swig would cause PythonEvent to be derived from object instead of Event | |||
| 2009-05-29 | request: add accessor and constructor for setting time other than curTick | Nathan Binkert | |
| 2009-05-28 | X86: Keep track of more descriptor state to accomodate KVM. | Gabe Black | |
| 2009-05-26 | types: add a type for thread IDs and try to use it everywhere | Nathan Binkert | |
| 2009-05-26 | X86: Really set up the GDT and various hidden/visible segment registers. | Gabe Black | |
| 2009-05-22 | util: mkblankimage.sh should be executable | Steve Reinhardt | |
| 2009-05-21 | build_opts: update ALPHA_FS cpu models | Korey Sewell | |
| 2009-05-20 | igbe: Fix descriptor cache bug. | Steve Reinhardt | |
| 2009-05-17 | includes: sort includes again | Nathan Binkert | |
| 2009-05-17 | includes: use base/types.hh not inttypes.h or stdint.h | Nathan Binkert | |
| 2009-05-17 | types: Move stuff for global types into src/base/types.hh | Nathan Binkert | |
| --HG-- rename : src/sim/host.hh => src/base/types.hh | |||
| 2009-05-13 | stats: tidy up the Distribution type a little bit | Nathan Binkert | |
| 2009-05-13 | stats: fancy is a bad name | Nathan Binkert | |
| 2009-05-13 | stats: clean up the code for printing stats | Nathan Binkert | |
| 2009-05-13 | mips-merge: merge hello world regress for inorder cpu | Korey Sewell | |
| w/latest changes | |||
| 2009-05-13 | inorder-regress: add hello MIPS_SE | Korey Sewell | |
| 2009-05-12 | ruby: deal with printf warnings and convert some to cprintf | Nathan Binkert | |
| 2009-05-12 | ruby: remove random uint typedef and use unsigned | Nathan Binkert | |
| 2009-05-12 | ruby: Make ruby's Map use hashmap.hh to simplify things. | Nathan Binkert | |
| 2009-05-12 | gcc: work around a bogus gcc error | Nathan Binkert | |
| 2009-05-12 | slicc: work around improper initialization of a global in slicc. | Nathan Binkert | |
| 2009-05-12 | slicc: clean up the slicc environment so things build properly on mac. | Nathan Binkert | |
| 2009-05-13 | mips_se: add cpu_models to build options | Korey Sewell | |
| 2009-05-13 | inorder-mips: Remove eaComp & memAcc; use 'visible' eaComp | Korey Sewell | |
| Inorder expects eaComp to be visible through StaticInst object. This mirrors a similar change to ALPHA... Needs to be done for SPARC and whatever other ISAs want to use InOrderCPU | |||
| 2009-05-13 | arch-mips: add regWidth constant to float regfile | Korey Sewell | |
| 2009-05-12 | cpus: add InOrderCPU to default build | Korey Sewell | |
| regressions need this so they build the model | |||
| 2009-05-12 | inorder-regress: missing regress config file | Korey Sewell | |
| regressions need to access this file to setup the InOrderCPU object | |||
| 2009-05-12 | alpha-isa: add mt.hh so it can compile with inorder | Korey Sewell | |
| 2009-05-12 | inorder-regress: add vortex ALPHA_SE | Korey Sewell | |
| 2009-05-12 | inorder-regress: add twolf ALPHA-SE | Korey Sewell | |
| 2009-05-12 | inorder-regress: add hello world | Korey Sewell | |
| 2009-05-12 | inorder-resources: delete events | Korey Sewell | |
| make sure unrecognized events in the resource pool are deleted and also delete resource events in destructor | |||
| 2009-05-12 | inorder-tlb-cunit: merge the TLB as implicit to any memory access | Korey Sewell | |
| TLBUnit no longer used and we also get rid of memAccSize and memAccFlags functions added to ISA and StaticInst since TLB is not a separate resource to acquire. Instead, TLB access is done before any read/write to memory and the result is checked before it's sent out to memory. * * * | |||
| 2009-05-12 | inorder-tlb: squash insts in TLB correctly | Korey Sewell | |
| TLB had a bug where if it was stalled and waiting , it would not squash all instructions older than squashed instruction correctly * * * | |||
| 2009-05-12 | inorder-faults: ignore unalign translation faults for prefetches | Korey Sewell | |
| 2009-05-12 | inorder-stc: update interface to handle store conditionals | Korey Sewell | |
| 2009-05-12 | inorder-float: Fix storage of FP results | Korey Sewell | |
| inorder was incorrectly storing FP values and confusing the integer/fp storage view of floating point operations. A big issue was knowing trying to infer when were doing single or double precision access because this lets you know the size of value to store (32-64 bits). This isnt exactly straightforward since alpha uses all 64-bit regs while mips/sparc uses a dual-reg view. by getting this value from the actual floating point register file, the model can figure out what it needs to store | |||
| 2009-05-12 | inorder-fetch: update model to use predecoder | Korey Sewell | |
| 2009-05-12 | inorder-mem: clean up allocation/deletion of requests/packets | Korey Sewell | |
| * * * | |||
| 2009-05-12 | inorder-mem: skeleton support for prefetch/writehints | Korey Sewell | |
| 2009-05-12 | inorder-o3: allow both to compile together | Korey Sewell | |
| allow InOrder and O3CPU to be compiled at the same time: need to make branch prediction filed shared by both models | |||
| 2009-05-12 | inorder-unified-tlb: use unified TLB instead of old TLB model | Korey Sewell | |
| 2009-05-12 | inorder-miscregs: Fix indexing for misc. reg operands and update ↵ | Korey Sewell | |
| result-types for better tracing of these types of values | |||
| 2009-05-12 | inorder/alpha-isa: create eaComp object visible to StaticInst through ISA | Korey Sewell | |
| Remove subinstructions eaComp/memAcc since unused in CPU Models. Instead, create eaComp that is visible from StaticInst object. Gives InOrder model capability of generating address without actually initiating access * * * | |||
| 2009-05-12 | inorder-bpred: edits to handle non-delay-slot ISAs | Korey Sewell | |
| Changes so that InOrder can work for a non-delay-slot ISA like Alpha. Typically, changes have to do with handling misspeculated branches at different points in pipeline | |||
| 2009-05-12 | inorder-alpha-port: initial inorder support of ALPHA | Korey Sewell | |
| Edit AlphaISA to support the inorder model. Mostly alternate constructor functions and also a few skeleton multithreaded support functions * * * Remove namespace from header file. Causes compiler issues that are hard to find * * * Separate the TLB from the CPU and allow it to live in the TLBUnit resource. Give CPU accessor functions for access and also bind at construction time * * * Expose memory access size and flags through instruction object (temporarily memAccSize and memFlags to get TLB stuff working.) | |||
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