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2016-05-19arm,dev: PL011 UART_FR read status enhancementBjoern A. Zeeb
Given we do not simulate a FIFO currently there are only two states we can be in upon read: empty or full. Properly signal the latter. Add and sort constants for states in the header file. Committed by Jason Lowe-Power <power.jg@gmail.com>
2016-05-19x86, dev: properly space the APIC registersBjoern A. Zeeb
Registers are 0x10 and not 0x8 apart. The latter leads to invalid calculations of index in array which in turn means that we will not find the interrupt we were looking (been notified) for in the OS. Committed by Jason Lowe-Power <power.jg@gmail.com>
2016-05-19dev, virtio: properly set PCI address space to use IOREGBjoern A. Zeeb
VirtIO spec < 1.0 demands IOREG to be used on PCI and not memory mapped. Set the correct bit on the PCI address accordingly. Committed by Jason Lowe-Power <power.jg@gmail.com>
2016-05-16gpu-compute: fix bug in GPUDynInst::isScalarRegister()Tony Gutierrez
2016-05-09scons: Rewrite git style hook installerAndreas Sandberg
The SCons script currently assumes that .git is a proper directory with all git meta data. This isn't the case if the working directory was checked out using git worktrees. In such case .git is a file with meta data telling git where the repository data is stored. This changeset updates changes the SConstruct file to rely on git rev-parse to get the real git directory. Change-Id: I3d0475eabc12e868193797067a88e540a9b6e927 Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Curtis Dunham <curtis.dunham@arm.com>
2016-05-09tests: Enable test running outside of gem5's source treeAndreas Sandberg
The learning gem5 scripts currently assumes that the current working directory is the root of gem5's source tree. This isn't necessarily the case when running the tests using gem5's new test runner. Change-Id: Ief569bbe77b1b3e2b0fb0e6c575fb0705bbba9b3 Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Curtis Dunham <curtis.dunham@arm.com>
2016-05-07tests: update EIO ref stats for removed cache statsSteve Reinhardt
Complaints about changes in EIO tests were due to reference files that still have removed cache stats from cset 11454:e55afadc4e19.
2016-05-06gpu-compute: fix spacing in GPUDynInst ctorTony Gutierrez
2016-05-06gpu-compute: fix uninitialized member bug in GPUDynInstTony Gutierrez
the n_reg field in the GPUDynInst is not currently set in the constructor. if it is not set externally, there are assertion failures that may occur if the random value it gets is just right. here we set it to 0 by default.
2016-05-06dev, arm: Update GIC to use GICv2 register namingAndreas Sandberg
The GICv2 has a new and slightly more consistent register naming. Update gem5's GIC register names to match the new documentation. Change-Id: I8ef114eee8a95bf0b88b37c18a18e137be78675a Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Curtis Dunham <curtis.dunham@arm.com>
2016-05-06arm: Update dts to work with the new HDLCD driverAndreas Sandberg
The dts files in system/arm/dt currently assume that an (unreleased) gem5-specific virtual encoder is used as a remote endpoint for the HDLCD. This driver won't be released as a more general virtual encoder is about to be posted on the Linux DRI devel list and this encoder has now been merged with gem5's kernel tree. This changeset updates gem5's dts files to use that encoder. Change-Id: Ic1a1be728efd31603752fdfba005b6dbdea42e7e Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Rene De Jong <rene.dejong@arm.com>
2016-04-28scons: emit correct message before installing git hookCurtis Dunham
Change-Id: Ied2e018a9a1b6db446edbaac871ac4efd795ec36 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
2016-04-28style: ignore test data in style checksCurtis Dunham
Change-Id: If797eaf3842b5c1604942bb60f091800ee814a2a Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
2016-04-28style: respect ignores for git commitCurtis Dunham
Previously it ignored the ignores for git but not Mercurial. Change-Id: I178fe879ebd268e863063eb9e30ec87e8ac8faec Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
2016-04-28style: improve compatibility with old git versionsCurtis Dunham
Older versions of git need the '=' to connect --diff-filter to its argument. Change-Id: Ic62057567db061684be88a7c2d80a6a5d4c11dcf
2016-04-28style: Don't include diff context in git style hookAndreas Sandberg
The git style hook currently includes a few lines of diff context when determining changed regions. This is undesirable as this triggers false positives when modifying existing files with a lot of style violations. This change sets the amount of context to 0, which is the default value when requesting staged regions from the git helper. Change-Id: Ibe03123e329ea0241281e104183a68d6c495b190 Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Nathanael Premillieu <nathanael.premillieu@arm.com>
2016-04-28tests: Remove stale reference output filesAndreas Sandberg
Remove test reference files that are not generated any more: * chair.cook.ppm: This file should be generated by eon and not mcf, so it shouldn't be included as an output from mcf. * system.pc.terminal: The terminal device has been renamed so this file is no longer generated. Change-Id: I3962efe1ff25479ca276115f7564eccb5fac8cf9 Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
2016-04-27arm: Remove BreakPCEvent on guest kernel panicAndreas Sandberg
The LinuxArmSystem class normally provides support for panicing gem5 if the simulated kernel panics. When this is turned off (default), gem5 uses a BreakPCEvent to provide a debugger hook into the simulator when the kernel crashes. This hook unconditionally kills gem5 with a SIGTRAP unless gem5 is compiled in fast mode. This is undesirable since the panic_on_panic param already provides similar functionality. Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
2016-04-27kvm, arm: Make GIC interrupt lines configurableAndreas Sandberg
Add support for overriding the number of interrupt lines in the ARM KvmGic. Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Radhika Jagtap <radhika.jagtap@arm.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
2016-04-27kvm, arm: Refactor KVM GIC deviceAndreas Sandberg
Factor out the kernel device wrapper from the KvmGIC and put it in a separate class. This will simplify a future kernel/gem5 hybrid GIC. Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Radhika Jagtap <radhika.jagtap@arm.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
2016-04-27dev: Fix incorrect terminal backlog handlingAndreas Sandberg
The Terminal device currently uses the peek functionality in gem5's circular buffer implementation to send existing buffered content on the terminal when a new client attaches. This functionallity is however not implemented correctly and re-sends the same block multiple time. Add the required functionality to peek with an offset into the circular buffer and change the Terminal::accept() implementation to send the buffered contents. Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Radhika Jagtap <radhika.jagtap@arm.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
2016-04-26ruby: Rename pkt to m_pkt so it may be accessed via SLICCMatthew Poremba
Allow usage of packet class in ruby for convenience purposes. This may be used to access members of the packet/request class (e.g., via helper functions) and/or push protocol specific information to the packets SenderState without needing to modify SLICC types and protocols in multiple locations.
2016-04-25tests: Add a basic memcheck regressionAndreas Hansson
This patch adds a simple regression that calls the existing memcheck.py script. --HG-- rename : tests/configs/learning-gem5-p1-simple.py => tests/configs/memcheck.py rename : tests/quick/se/70.tgen/test.py => tests/quick/se/51.memcheck/test.py
2016-04-21tests: Update learning gem5 tests scripts with copyrightJason Power
2016-04-21stats: Update stats to reflect cache changesAndreas Hansson
Removed unused stats, now counting WriteLineReq, and changed how uncacheable writes are handled while responses are outstanding.
2016-04-21mem: Include WriteLineReq in cache demand statsAndreas Hansson
Somehow the WriteLineReq were never added to the list of commands considered demand.
2016-04-21mem: Remove unused cache statsAndreas Hansson
Prune cache stats that are never actually used.
2016-04-21mem: Deallocate all write-queue entries when sentAndreas Hansson
This patch removes the write-queue entry tracking previously used for uncacheable writes. The write-queue entry is now deallocated as soon as the packet is sent. As a result we also forego the stats for uncacheable writes. Additionally, there is no longer a need to attach the write-queue entry to the packet.
2016-04-21mem: Align downstream cache packet creation in atomic and timingAndreas Hansson
This patch makes the control flow more uniform in atomic and timing, ultimately making the code easier to understand.
2016-04-21config: Add missing point of coherency to memcheck scriptAndreas Hansson
Bring in line with changes to the XBar class.
2016-04-18scons: Fix Python 2.6 compatibilityAndreas Sandberg
Don't use Python 2.7-style with statements in the SConstruct file.
2016-04-18style: Fix Python 2.6 compatibilityAndreas Sandberg
The style checker code needs to disable autojunk when diffing source files using Python's difflib. Support for this was only introduced in Python 2.7, which leads to a TypeError exception on older Python version. This changeset adds a fallback mechanism for old Python versions.
2016-04-15ruby: Fix block_on behaviorJoel Hestness
Ruby's controller block_on behavior aimed to block MessageBuffer requests into SLICC controllers when a Locked_RMW was in flight. Unfortunately, this functionality only partially works: When non-Locked_RMW memory accesses are issued to the sequencer to an address with an in-flight Locked_RMW, the sequencer may pass those accesses through to the controller. At the controller, a number of incorrect activities can occur depending on the protocol. In MOESI_hammer, for example, an intermediate IFETCH will cause an L1D to L2 transfer, which cannot be serviced, because the block_on functionality blocks the trigger queue, resulting in a deadlock. Further, if an intermediate store arrives (e.g. from a separate SMT thread), the sequencer allows the request through to the controller, and the atomicity of the Locked_RMW may be broken. To avoid these problems, disallow the Sequencer from passing any memory accesses to the controller besides Locked_RMW_Write when a Locked_RMW is in- flight.
2016-04-15arm,dev: remove PMU assertion hit on resetBjoern A. Zeeb
Remve the assertion that we always need to add a delta larger than zero as that does not seem to be true when we hit it in the 'PMU reset cycle counter to zero' case. Committed by Jason Lowe-Power <power.jg@gmail.com>
2016-04-15mem: FreeBSD does not provide MAP_NORESERVE eitherBjoern A. Zeeb
Like OS X, FreeBSD does not support MAP_NORESERVE. Handle accordingly and update comment. Committed by Jason Lowe-Power <power.jg@gmail.com>
2016-04-15misc: Bugfix in TLM memInhibit CommandAbdul Mutaal Ahmad
memInhibitAsserted() has been removed from packet.hh. This change has been reflected in TLM based SystemC memory. This patch also adds a number of panics asserting the SystemC memory only sees requests it expects. Committed by Jason Lowe-Power <power.jg@gmail.com>
2016-04-14dist: config file for distributed switchMohammad Alian
Distributed gem5 is the result of the convergence effort between multi-gem5 and pd-gem5. It relies on the base multi-gem5 infrastructure for packet forwarding, synchronisation and checkpointing but combines those with the elaborated network switch model from pd-gem5.
2016-04-13misc: Fix issues flagged by gcc 6Andreas Hansson
A few warnings (and thus errors) pop up after being added to -Wall: 1. -Wmisleading-indentation In the auto-generated code there were instances of if/else blocks that were not indented to gcc's liking. This is addressed by adding braces. 2. -Wshift-negative-value gcc is clever enougn to consider ~0 a negative constant, and rightfully complains. This is addressed by using mask() which explicitly casts to unsigned before shifting. That is all. Porting done.
2016-04-12misc: Appease clang...againAndreas Hansson
Once again, clang is having issues with recently committed code. Unfortunately HSAIL_X86 is still broken.
2016-04-09stats: Match current behaviourAndreas Hansson
Small changes to the branch predictor and BTB caused stats changes throughout.
2016-04-08stats: update stats for thermals, indirect BPCurtis Dunham
2016-04-07mem: Add priority to QueuedPrefetcherRekai Gonzalez Alberquilla
Queued prefetcher entries now count with a priority field. The idea is to add packets ordered by priority and then by age. For the existing algorithms in which priority doesn't make sense, it is set to 0 for all deferred packets in the queue.
2016-04-07mem: Handful extra features for BasePrefetcherRekai Gonzalez Alberquilla
Some common functionality added to the base prefetcher, mainly dealing with extracting the block address, page address, block index inside the page and some other information that can be inferred from the block address. This is used for some prefetching algorithms, and having the methods in the base, as well as the block size and other information is the sensible way.
2016-04-07mem: Add Program Counter to MemTraceProbeVictor Garcia
2015-05-27mem: Add unused prefetch counter in cachesRekai Gonzalez Alberquilla
Added stat to the cache to account for HardPF'ed blocks that are evicted before being referenced (over-prefetching).
2016-04-07mem: Remove threadId from memory request classMitch Hayenga
In general, the ThreadID parameter is unnecessary in the memory system as the ContextID is what is used for the purposes of locks/wakeups. Since we allocate sequential ContextIDs for each thread on MT-enabled CPUs, ThreadID is unnecessary as the CPUs can identify the requesting thread through sideband info (SenderState / LSQ entries) or ContextID offset from the base ContextID for a cpu. This is a re-spin of 20264eb after the revert (bd1c6789) and includes some fixes of that commit.
2016-04-05cpu: Implement per-thread GHRsMitch Hayenga
Branch predictors that use GHRs should index them on a per-thread basis. This makes that so. This is a re-spin of fb51231 after the revert (bd1c6789).
2016-04-05cpu: Add an indirect branch target predictorMitch Hayenga
This patch adds a configurable indirect branch predictor that can be indexed by a combination of GHR and path history hashes. Implements the functionality described in: "Target prediction for indirect jumps" by Chang, Hao, and Patt http://dl.acm.org/citation.cfm?id=264209 This is a re-spin of fb9d142 after the revert (bd1c6789).
2016-04-05cpu: Fix BTB threading oversightMitch Hayenga
The extant BTB code doesn't hash on the thread id but does check the thread id for 'btb hits'. This results in 1-thread of a multi-threaded workload taking a BTB entry, and all other threads missing for the same branch missing.
2016-04-06misc: Bail out of DVFS dot if we cannot resolve the domainsSascha Bischoff
This changeset updates the dot output to bail out if it is unable to resolve the voltage or clock domains (which will cause it to raise an AttributeError). Additionally, the DVFS dot output is disabled by default for speed purposes. Minor fixup for 0aeca8f.
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