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SConscript:
Added more files to compile: dev/pcifake.cc, dev/isa_fake.cc, kern/freebsd/freebsd_system.cc, kern/freebsd/freebsd_events.cc.
arch/alpha/isa_traits.hh:
Added constant for argument register 2 as it is needed by FreebsdSystem::doCalibrateClocks().
cpu/exec_context.hh:
cpu/o3/alpha_cpu.hh:
Replaced htoa()s with gtoh() and htog().
cpu/o3/fetch_impl.hh:
cpu/simple/cpu.cc:
Replaced htoa() with gtoh().
dev/disk_image.cc:
Replaced htoa()s with letoh()s.
dev/ide_ctrl.cc:
Got rid of magic numbers.
Added IdeChannel and IdeRegType type names where necessary.
dev/ide_ctrl.hh:
Got rid of unnecessary macros.
Changed RegType_t to IdeRegType.
Changed bmi_regs to allow accessing registers by name instead of just by array index.
Added IdeChannel enum type to use in place of bool variables which were used to specify IDE channel.
dev/ide_disk.cc:
Rewrote IdeDisk::read and IdeDisk::write functions to specify registers by name instead of indexing through an array.
dev/ide_disk.hh:
Updated command register struct.
dev/ns_gige.cc:
dev/ns_gige.hh:
Made ReadConfig and WriteConfig begin with a lower-case letter.
writeConfig() now takes a pointer to data as a parameter instead of a copy of data.
dev/pciconfigall.cc:
writeConfig() now takes a pointer to data as a parameter instead of a copy of data.
dev/pcidev.cc:
Cleaned up readConfig() and writeConfig() functions.
dev/pcidev.hh:
Added macros to make code that works with the BARs (base adress registers) more readable. writeConfig() now takes a pointer to data.
dev/pcireg.h:
Changed PCIConfig struct to make accessing elements more straight forward. Removed type 1 (for PCI-to-PCI bridges) PCI configuration space struct since it is not used.
dev/rtcreg.h:
Added macros for bit fields in RTC status registers A & B.
dev/sinic.cc:
Function name change: WriteConfig --> writeConfig.
writeConfig() now takes a pointer to data instead of a copy of data.
The accessing of elements of PCIConfig structure is updated.
dev/sinic.hh:
Function name change: WriteConfig --> writeConfig.
writeConfig() now takes a pointer to data instead of a copy of data.
dev/tsunami_io.cc:
Added implementation of new RTC and PIT classes.
dev/tsunami_io.hh:
Added classes for RTC and PIT modules.
dev/tsunamireg.h:
Added macros for DMA ports used by Tsunami-Tru64.
dev/uart8250.cc:
Got rid of a magic number.
Transmit (Tx) interrupts should clear upon a read of the Interrupt ID register.
dev/uart8250.hh:
Added comments and macros dealing with the UART Interrupt ID register.
kern/linux/linux_system.cc:
Replaced htoa() with htog().
python/m5/objects/Pci.py:
PciFake is a python class for Pci Devices that do nothing.
python/m5/objects/Tsunami.py:
TsunamiFake was renamed as IsaFake.
sim/system.cc:
Replaced htoa()s with htog()s.
dev/isa_fake.cc:
New BitKeeper file ``dev/isa_fake.cc''
TsunamiFake was renamed as IsaFake.
dev/isa_fake.hh:
New BitKeeper file ``dev/isa_fake.hh''
TsunmaiFake was renamed as IsaFake.
dev/pitreg.h:
New BitKeeper file ``dev/pitreg.h''
Useful macros for working with PIT (Periodic Interval Timer) registers.
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python/m5/config.py:
Fix error message.
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Involves adding functional memory param
(for full-system mode only, for now).
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Add license.
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dev/ide_atareg.h:
Need endian.h for LITTLE_ENDIAN.
sim/syscall_emul.hh:
Need to include sys/fcntl.h to get O_BINARY.
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sim/system.cc:
Add a global variable that will tell the remote debugger to
wait when a given CPU is is registered.
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dev/ide_ctrl.cc:
Initialize variables to zero to avoid uninitialized usage.
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Make the AlphaConsole calculate the number of CPUs instead
of passing that in as a parameter.
cpu/base.cc:
pass the desired cpu_id into registerExecContext, offsetting it
by the thread number. a cpu_id of -1 means that it should be
generated for you.
cpu/base.hh:
Take the cpu_id as a parameter
cpu/o3/alpha_cpu_builder.cc:
cpu/simple/cpu.cc:
Accept the cpu_id as a parameter
while we're here, let's remove the multiplier since it is
not used.
dev/alpha_console.cc:
don't take the number of CPUs as a parameter. Calculate it from
the system based on the number of CPUs that have been registered.
move init() code to startup() to ensure that all CPUs are registerd.
dev/alpha_console.hh:
python/m5/objects/AlphaConsole.py:
don't take the number of CPUs as a parameter.
move init() code to startup() to ensure that all CPUs are registerd.
python/m5/objects/BaseCPU.py:
take the cpu_id as a parameter. Default it to -1 which means
that it will be generated.
sim/system.cc:
allow the registerExecContext functioin to take a desired
cpu_id as a parameter. Check to ensure that the id isn't
already used. Accept -1 as a request to have an id assigned.
sim/system.hh:
keep track of the number of registered exec contexts.
provide a function for accessing the number of exec contexts
that checks to ensure that they are all registered correctly.
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code into a function that can be called by the AlphaConsole class.
AlphaConsole will pass in its address.
arch/alpha/ev5.hh:
Move Phys2K0Seg to ev5.hh and fixup the TSUNAMI uncacheable
bits so that they will be converted correctly.
dev/alpha_access.h:
Do not hard code the location of the AlphaConsole
dev/alpha_console.cc:
fixup #includes
tell the system where the alpha console is
sim/system.hh:
Provide a function that will tell the system where the AlphaAccess
structure (device) lives
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instead of compiling it into the console version
dev/alpha_access.h:
move serialization stuff to alpha_console.hh
define the ALPHA_ACCESS_BASE in m5 instead of in console.c and
have m5 pass the value to the console
dev/alpha_console.cc:
dev/alpha_console.hh:
Move serialization stuff into a derived class of AlphaAccess
sim/system.cc:
pass the value of ALPHA_ACCESS_BASE to the console code via
the m5AlphaAccess console variable.
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for accessing physical packets.
Add support for tap devices found on linux and bsd.
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dev/alpha_access.h:
Update the ALPHA_ACCESS_VERSION
move typedefs to this file since they're only used here.
dev/alpha_console.cc:
formatting
sim/system.cc:
xxm -> m5
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the nsgige state machine can run. The frequency is of the actual
state transitions, and not the rate of what underlying
instructions might run at.
dev/ns_gige.cc:
Implement a state machine clock that acutally limits how fast
the state machine can run. After each state transition, a
variable is kept to hold the next state transition until the
next clock. The frequency is of the actual state transitions,
and not the rate of what underlying instructions might run at.
dev/ns_gige.hh:
Add back the rxKickEvent and txKickEvent events.
python/m5/objects/Ethernet.py:
Default the state machine clock to '0ns' so the default
behaviour doesn't change when we actually implement the
state machine clock.
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Fixed printing so the tokenizer in m5 doesn't get confused
Expanded NullSimObject so it could be used as an element in a VectorParam
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object and get rid of the ParamContext that each used to have.
python/m5/objects/Root.py:
Add max_time and progress_interval to the Root object
sim/root.cc:
Add max_time and progress_interval to the Root object. These
parameters used to be in their own contexts in sim_events.cc
sim/sim_events.cc:
Get rid of the ParamContext for max cycles and the progress
event. Move the functionality to the Root object
sim/sim_events.hh:
Move ProgressEvent declaration to the header so that it can
be used in other files.
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into ziff.eecs.umich.edu:/z/binkertn/research/m5/head
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base/str.cc:
Fix tokenize so that it doesn't behave incorrectly when there
are empty strings.
test/tokentest.cc:
Clean up the test function so it's easier to see what's going on
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when I added them to the global list...
SConscript:
Remove opt_cpu and trace_cpu from syscall_emulation_sources
to avoid double definition.
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(from a trace replay).
SConscript:
Compile in trace-reader CPUs.
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into zizzer.eecs.umich.edu:/z/stever/bk/m5
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clean up debugging a bit
dev/ns_gige.cc:
little bit of formatting
don't break in the debugger if a packet is dropped when the
receiver is disabled since it can realistically happen
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into zizzer.eecs.umich.edu:/z/stever/bk/m5
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base/mysql.hh:
Add support for for transactions
base/stats/mysql.cc:
get rid of table locking and start using transactions
base/stats/mysql_run.hh:
setup()/remove()/cleanup() should be protected, not private
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release versions of m5, m5-test, and ext.
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Add FALRU & IIC back in.
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get rid of python_file param
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kern/linux/linux_threadinfo.hh:
kern/linux/sched.hh:
changed names slightly
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SConscript:
Get rid of prefetch & split cache files (temporarily).
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into crampon.my.domain:/z/binkertn/research/m5/head
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are ours
arch/alpha/alpha_linux_process.hh:
arch/alpha/alpha_tru64_process.hh:
base/loader/object_file.cc:
base/loader/object_file.hh:
sim/process.cc:
sim/process.hh:
remove $Id$ string
cpu/ozone/cpu.cc:
cpu/ozone/cpu_impl.hh:
cpu/ozone/ea_list.cc:
cpu/ozone/ea_list.hh:
kern/linux/sched.hh:
kern/linux/thread_info.hh:
Add M5 Copyright
cpu/trace/opt_cpu.cc:
dev/rtcreg.h:
nit
kern/linux/aligned.hh:
kern/linux/hwrpb.hh:
util/oprofile-top.py:
util/stats/db.py:
util/stats/dbinit.py:
util/stats/display.py:
util/stats/info.py:
util/stats/print.py:
util/stats/stats.py:
Cleanup copyright
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