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2009-11-18m5: Added the default m5out directory to the hg ignore listBrad Beckmann
2009-11-18ruby: The persistent table files from GEMSBrad Beckmann
These files are need by the MOESI_CMP_token protocol.
2009-11-18ruby: MOESI hammer support for DMA reads and writesBrad Beckmann
2009-11-18ruby: Added a memory controller feature to MOESI hammerBrad Beckmann
2009-11-18ruby: Hammer ruby configuration supportBrad Beckmann
2009-11-18ruby: Changes necessary to get the hammer protocol to work in GEM5Brad Beckmann
2009-11-18ruby: added the original hammer protocols from old rubyBrad Beckmann
2009-11-18ruby: returns the number of LLC needed for broadcastBrad Beckmann
Added feature to CacheMemory to return the number of last level caches. This count is need for broadcast protocols such as MOESI_hammer.
2009-11-18ruby: cache configuration fix to use bytesBrad Beckmann
Changed cache size to be in bytes instead of kb so that testers can use very small caches and increase the chance of writeback races.
2009-11-18ruby: fix CacheMemory destructorBrad Beckmann
2009-11-18ruby: split CacheMemory.hh into a .hh and a .ccBrad Beckmann
2009-11-18ruby: Added default names to message buffersBrad Beckmann
Added default names to message buffers created by the simple network.
2009-11-18ruby: slicc method error fixBrad Beckmann
Added error message when a method call is not supported by an object.
2009-11-18ruby: slicc action error fixBrad Beckmann
Small fix to the State Machine error message when duplicate actions are defined.
2009-11-18ruby: slicc state machine error fixesBrad Beckmann
Added error messages when: - a state does not exist in a machine's list of known states. - an event does not exist in a machine - the actions of a certain machine have not been declared
2009-11-18ruby: Removed unused action z_stallBrad Beckmann
2009-11-18m5: Added option to take a checkpoint at the end of simulationBrad Beckmann
2009-11-18m5: Fixed bug in atomic cpu destructorBrad Beckmann
2009-11-18ruby: fixed dma mi example to work with multiple dma portsBrad Beckmann
2009-11-18m5: removed master and slave deletions.Brad Beckmann
The unresolved destructor call caused a seg fault when called.
2009-11-18m5: fixed destructor to deschedule the tickEvent and eventBrad Beckmann
2009-11-18ruby: getPort function fixBrad Beckmann
Fixed RubyMemory::getPort function to not pass in a -1 for the idx parameter
2009-11-18ruby: Fixed Directory memory destructorBrad Beckmann
2009-11-18m5: Moved profile option since Simulation depends on it.Brad Beckmann
2009-11-18m5: Added isValidSrc and isValidDest calls to packet.hhBrad Beckmann
2009-11-18ruby: included ruby config parameter ports per coreBrad Beckmann
Slightly improved the major hack need to correctly assign the number of ports per core. CPUs have two ports: icache + dcache. MemTester has one port.
2009-11-18ruby: Added error check for openning the ruby config fileBrad Beckmann
2009-11-18ruby: Support for merging ALPHA_FS and rubyBrad Beckmann
Connects M5 cpu and dma ports directly to ruby sequencers and dma sequencers. Rubymem also includes a pio port so that pio requests and be forwarded to a special pio bus connecting to device pio ports.
2009-11-18ruby: Added more info to bridge error messageBrad Beckmann
2009-11-18ruby: Ruby 64-bit address output fixes.Brad Beckmann
2009-11-18ruby: Ruby destruction fix.Brad Beckmann
2009-11-18ruby: Ruby debug print fixes.Brad Beckmann
2009-11-18ruby: Ruby memtest python script.Brad Beckmann
2009-11-17ARM: Begin implementing CP15Ali Saidi
2009-11-17ARM: Differentiate between LDM exception return and LDM user regs.Ali Saidi
2009-11-17ARM: Boilerplate full-system code.Ali Saidi
--HG-- rename : src/arch/sparc/interrupts.hh => src/arch/arm/interrupts.hh rename : src/arch/sparc/kernel_stats.hh => src/arch/arm/kernel_stats.hh rename : src/arch/sparc/stacktrace.cc => src/arch/arm/stacktrace.cc rename : src/arch/sparc/system.cc => src/arch/arm/system.cc rename : src/arch/sparc/system.hh => src/arch/arm/system.hh rename : src/dev/sparc/T1000.py => src/dev/arm/Versatile.py rename : src/dev/sparc/t1000.cc => src/dev/arm/versatile.cc rename : src/dev/sparc/t1000.hh => src/dev/arm/versatile.hh
2009-11-16imported patch isa_fixes2.diffAli Saidi
2009-11-15ARM: Make the exception return form of ldm restore CPSR.Gabe Black
2009-11-15ARM: Create a new type of load uop that restores spsr into cpsr.Gabe Black
2009-11-14ARM: Check in the actual change from the last commit.Gabe Black
The last commit was somehow empty. This was what was supposed to go in it.
2009-11-14ARM: Switch the immediate and register versions of msr.Gabe Black
These were accidently transposed. This change straightens them out.
2009-11-14ARM: Fix up the implmentation of the msr instruction.Gabe Black
2009-11-14ARM: Define a mask to differentiate purely CPSR bits from CondCodes bits.Gabe Black
2009-11-14ARM: Add a bitfield to indicate if an immediate should be used.Gabe Black
2009-11-14ARM: Write some functions to write to the CPSR and SPSR for instructions.Gabe Black
2009-11-14ARM: Fix up the implmentation of the mrs instruction.Gabe Black
2009-11-14ARM: More accurately describe the effects of using the control operands.Gabe Black
2009-11-14ARM: Hook up the moded versions of the SPSR.Gabe Black
These registers can be accessed directly, or through MISCREG_SPSR which will act as whichever SPSR is appropriate for the current mode.
2009-11-14SE: Fix SE mode OS X compilation.Ali Saidi
2009-11-14ARM: Move around decoder to properly decode CP15Ali Saidi