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2008-01-23X86: Put an SMBios/DMI table in memory.Gabe Black
This is basically just the header right now, but there's an untested mechanism in place to fill out the table and make sure everything is updated correctly. --HG-- extra : convert_revision : c1610c0dfa211b7e0d091a04133695d84f500a1c
2008-01-23X86: Optomize the bit scanning instruction microassembly a little. More can ↵Gabe Black
be done. --HG-- extra : convert_revision : 3cf6e972f0e41e3529a633ecbb31289e1bd17f0f
2008-01-22X86: Implement and attach the BSR and BSF instructions.Gabe Black
--HG-- extra : convert_revision : be7e11980092e5d1baff0e05d4ec910305966908
2008-01-21X86: Fill out group17 in the decoder.Gabe Black
--HG-- extra : convert_revision : 66ab9c0fc3086f66e3d6d82d47964ecf406c3a8a
2008-01-21X86: Use the existing boot_osflags instead of duplicating it.Gabe Black
--HG-- extra : convert_revision : e04e438d7d261a61c52b946c23cd126ed648814a
2008-01-16Update long o3 regressions for o3 change in previous changesetAli Saidi
--HG-- extra : convert_revision : 00242105076eb4466cce21038858f2b9d20b2fe2
2008-01-15Update O3 ref outputs: very minor stats change due to previous cset.Steve Reinhardt
(from Steve on behalf of m5test). --HG-- extra : convert_revision : 696efdaa3dd7680dfc9c797a6a46a5053238c7d2
2008-01-14The reason is that the event is supposed to put the instructions ready to ↵Ke Meng
execute for next cycle. And the FUCompletion event has a lower priority than CPU tick event. It is called after the iew->tick() for current cycle has already been executed and the issueToExecuteQueue has already advanced this time. And assume the issueToExecuteLatency is 1, to catch up, the increasement should be made at access(-1) instead of access(0). Otherwise I found it could increase the actual op_latency of the instructions to execute by 1 cycle and potentially put the simulated CPU into a permanent idle state. Signed-off by: Ali Saidi <saidi@eecs.umich.edu> --HG-- extra : convert_revision : dafc16814383e8e8f8320845edf6ab2bcfed1e1d
2008-01-12X86: Redo the bit test instructions.Gabe Black
--HG-- extra : convert_revision : 433c2a9f3675ed02f3be5ce759a440f2686d2ccd
2008-01-12X86: Fix the wrmsr instruction.Gabe Black
--HG-- extra : convert_revision : 12bc7e71226ebafb8eedadf6a3db82929e15e722
2008-01-12X86: Make the effective segment base shadow the regular one, not the selector.Gabe Black
--HG-- extra : convert_revision : 498c7c16d664c784b196885b1f35c3c6386c9cfc
2008-01-12X86: Make the IO ports work using extra physical address lines. Add a serial ↵Gabe Black
port. --HG-- extra : convert_revision : a14cb4fc9afedfc0ff58b11a7f8fb5516d462cc6
2008-01-12X86: Fix the general IO instructions dataSize.Gabe Black
--HG-- extra : convert_revision : 9774a52cb6a8e7632d1b1dc0706e5791cc18d238
2008-01-06Temporary fix for ll/sc bug see flyspray task for more info:Geoffrey Blake
http://www.m5sim.org/flyspray/task/197 Signed-off by: Ali Saidi <saidi@eecs.umich.edu> --HG-- extra : convert_revision : cdeece7e3163de9abf2c6c7435f1bc93570fab81
2008-01-02Very minor memtest regression stats changes from recent coherence bug fixes.Steve Reinhardt
--HG-- extra : convert_revision : 5e7f8ce91ea8f98e6503ac9e10aae68c62f9e510
2008-01-02Add ReadRespWithInvalidate to handle multi-level coherence situationSteve Reinhardt
where we defer a response to a read from a far-away cache A, then later defer a ReadExcl from a cache B on the same bus as us. We'll assert MemInhibit in both cases, but in the latter case MemInhibit will keep the invalidation from reaching cache A. This special response tells cache A that it gets the block to satisfy its read, but must immediately invalidate it. --HG-- extra : convert_revision : f85c8b47bb30232da37ac861b50a6539dc81161b
2008-01-02Mark cache-to-cache MSHRs as downstreamPending when necessary.Steve Reinhardt
Don't mark upstream MSHR as pending if downstream MSHR is already in service. --HG-- extra : convert_revision : e1c135ff00217291db58ce8a06ccde34c403d37f
2008-01-02Don't DPRINTF in the middle of a PrintReq.Steve Reinhardt
--HG-- extra : convert_revision : 6358c014d14a19a34111c39827b05987507544bb
2008-01-02Bug fix: functional cache port now needs otherPort set.Steve Reinhardt
--HG-- extra : convert_revision : fb007df73a77535a5dba19341f7b0b32e8c99548
2008-01-02Additional comments and helper functions for PrintReq.Steve Reinhardt
--HG-- extra : convert_revision : 7eadf9b7db8c0289480f771271b6efe2400006d4
2008-01-02Add functional PrintReq command for memory-system debugging.Steve Reinhardt
--HG-- extra : convert_revision : 73b753e57c355b7e6873f047ddc8cb371c3136b7
2008-01-02Fix formatting and comments in cache_impl.hhSteve Reinhardt
--HG-- extra : convert_revision : 26d71cca5420ad03e16bf174e15dabe7f902da41
2008-01-01SPARC: Fix a bug where the TLB would match against the wrong entries.Gabe Black
--HG-- extra : convert_revision : 631b3b6a1416121b54bd9717ca1cdccdd5b8a1eb
2007-12-18Checkpointing: Fix a bug in the simulation script when restoring without ↵Ali Saidi
standard switch and change some ifs to work with the default port since every port is now connected to something. --HG-- extra : convert_revision : 72507cf13e58465291b0dce6322e853bee5a2b89
2007-12-16CPU: Update where the simple cpus read their cpu id from the thread context ↵Ali Saidi
to init() to make sure they read the right value. This fixes a bug with multi-processor full-system configurations. --HG-- extra : convert_revision : 4f2801967a271b43817d88e147c2f80c4480b2c3
2007-12-11Fix minor bug in util/style.pySteve Reinhardt
--HG-- extra : convert_revision : d37accc884c2967d87dd267debab5afeb8b6ed85
2007-12-03X86: Update the parser reference output which has mysteriously changed again?Gabe Black
--HG-- extra : convert_revision : 9b1439096509633d6e9b5bc0c661608f40a63c5f
2007-12-03X86: Please excuse my dear Aunt Sally. (precedence bug)Gabe Black
--HG-- extra : convert_revision : 9ad4f31e7a962c3177896bcbfb93e2e54720d117
2007-12-02X86: Make sure the memory index is calculated using the address size for bit ↵Gabe Black
test instructions. --HG-- extra : convert_revision : 9634675857dae53b5e79e49267c864a0265afde1
2007-12-02X86: Fix a copy/paste mistake where the bit test instructions were using an ↵Gabe Black
immediate where they should use a register. --HG-- extra : convert_revision : b0ee80e4c7fdb58a1eb85b3bcc82a0cdaa93330a
2007-12-02X86: Make the page not present panic more descriptive.Gabe Black
--HG-- extra : convert_revision : 9360e47adb61e164ac218f2ea231eaa60bf3229d
2007-12-02X86: Start setting up the real mode data structure.Gabe Black
--HG-- extra : convert_revision : ba6d4939d4d58da5586655c83f1617f47dc7e359
2007-12-02X86: Make the 0xA0-0xA3 versions of mov use the right sized immediates.Gabe Black
--HG-- extra : convert_revision : a702403de29772618abb5bd5c5555279d91bdd59
2007-12-01X86: Add in a missing "break".Gabe Black
--HG-- extra : convert_revision : 2e48d8b0292bc3b78e4caa27dec20113d40e7d74
2007-12-01X86: Actually do something for the MiscRegFile clear function.Gabe Black
--HG-- extra : convert_revision : 36f8abaa9d09700d8ba9e09b4a10fa4dce580f36
2007-12-01X86: Move startup code to the system object to initialize a Linux system.Gabe Black
--HG-- extra : convert_revision : a4796c79f41aa8b8f38bf2f628bee8f1b3af64be
2007-12-01X86: Add a missing microcode file to the sconscript.Gabe Black
--HG-- extra : convert_revision : 6da8a67e07bada169abf7f10aded8a90d4e63eae
2007-12-01X86: Fix a copy paste error in the bts microcode.Gabe Black
--HG-- extra : convert_revision : c4ac007d35ac13211f9816f1104c84f2b447ddba
2007-12-01X86: Implement mov from control register.Gabe Black
--HG-- extra : convert_revision : c8280f0686a3ae6d5c405327540ad15a3a5531f9
2007-12-01X86: First crack at far returns. This is grossly approximate.Gabe Black
--HG-- extra : convert_revision : 23da0338af1f7663ae5ddf2289fb45dd32f37c42
2007-12-01X86: Reorganize segmentation and implement segment selector movs.Gabe Black
--HG-- extra : convert_revision : 553c3ffeda1f5312cf02493f602e7d4ba2fe66e8
2007-12-01X86: Make the "fault" microop predicated.Gabe Black
--HG-- extra : convert_revision : ded34133afcd6af1f55b8991b82bad45258069d3
2007-12-01X86: Implement the LIDT instruction.Gabe Black
--HG-- extra : convert_revision : 380515e985318311632e00b13000585afb052e3b
2007-12-01X86: Implement the lgdt instruction.Gabe Black
--HG-- extra : convert_revision : d1698a82df3c57cc9bbf8d5d190f271bfc7cb2e4
2007-12-01X86: Implement wrbase and wrlimit for loading pseudo descriptors.Gabe Black
--HG-- extra : convert_revision : fe03c4aed95ef12773e80cdb3d9cff68a2b20f02
2007-12-01X86: Separate the effective seg base and the "hidden" seg base.Gabe Black
--HG-- extra : convert_revision : 5fcb8d94dbab7a7d6fe797277a5856903c885ad4
2007-11-30SPARC: Fixes for invalidateAll and demapAll in the SPARC TLBs.Gabe Black
--HG-- extra : convert_revision : 8de6c60b0e3e725eac11047a9d9888097dd359ff
2007-11-29SPARC: Fix 32 bit register window flushing endian conversion.Gabe Black
--HG-- extra : convert_revision : be91d6fecb44a85e983343704a098b456948af8a
2007-11-29SPARC: Fix the initial stack to match what the Linux kernel does.Gabe Black
--HG-- extra : convert_revision : a4451710d8463e52227fd8f760ab737ea8f404b5
2007-11-29SPARC: Combine the 64 and 32 bit process initialization code.Gabe Black
Alignment is done as it was for 32 bit processes. --HG-- extra : convert_revision : 9368ad40dcc7911f8fc7ec1468c6a28aa92d196f
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-29 18:57:39 +0000