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2006-05-25Fix stat typo.Kevin Lim
--HG-- extra : convert_revision : f23d8c50f586fb8f25d4ce992730213f0c301b0f
2006-05-25Fix up kernel stats, allow them to not be used as well.Kevin Lim
arch/alpha/ev5.cc: Fix up some stuff I missed in the last kernel stats checkin. cpu/checker/cpu.cc: Allow the checker to disable its kernel stats. cpu/cpu_exec_context.cc: Allow CPUExecContext to be created without kernelStats. cpu/cpu_exec_context.hh: Allow CPUExecContext to be created without kernelStats. Default usage leaves kernelStats on. --HG-- extra : convert_revision : 8ed5bffd3a5b6275baa07fb4ea385eeab1a0456a
2006-05-24Support new flags now used instead of flags in decoder.isa.Kevin Lim
cpu/ozone/front_end_impl.hh: cpu/ozone/lw_back_end_impl.hh: cpu/ozone/lw_lsq_impl.hh: Support new flags added in. --HG-- extra : convert_revision : 2e756fd1913cf600650afc39dd715d59b9b89c42
2006-05-23Merge ktlim@zizzer:/bk/m5Kevin Lim
into zamp.eecs.umich.edu:/z/ktlim2/clean/m5-o3 --HG-- extra : convert_revision : 804302a5edb9d908808861f7f54a4f3cbb22830c
2006-05-23Updates to isa parser to make it see dependencies properly with the new scanner.Kevin Lim
arch/alpha/isa/main.isa: Use automatic path includes thanks to updates to isa parser. arch/isa_parser.py: Pull changes to isa parser from newmem into m5. This fixes a bug where the files include in main.isa were not being included as dependencies properly. --HG-- extra : convert_revision : 8ef1e2e1a64e7a5762baf7a09abc8665d7c2f688
2006-05-23Merge ktlim@zizzer:/bk/m5Kevin Lim
into zamp.eecs.umich.edu:/z/ktlim2/clean/m5-o3 --HG-- extra : convert_revision : 0a6140f3f5e7c454981c5aa2b221224f076e50eb
2006-05-23Rework how instructions are scheduled and executed.Kevin Lim
The "execute" portion of IEW is really just the last cycle of execution, at which point execute() gets called. Execution begins inside the IQ, when it schedules FUs for specific instructions. As a result, the Execute stage should just pull all completing instructions out of the IQ stage and execute them. Limiting the number of writebacks outstanding must still be done. cpu/o3/iew_impl.hh: Rework how instructions are scheduled and executed. There shouldn't be a specific "width" from issue to execute because issue does the scheduling of the functional units (really the beginning of the execution). cpu/o3/inst_queue.hh: cpu/o3/inst_queue_impl.hh: Rework how instructions are scheduled and executed. --HG-- extra : convert_revision : bbf1a8a4c0a2f2a938bdd78d74493048fd3b4b55
2006-05-23Cleanup checker.Kevin Lim
cpu/checker/cpu.cc: Cleanup checker, give more useful warning messages. Also fix bug cpu/checker/cpu.hh: Cleanup checker, use forward declaration instead of include. --HG-- extra : convert_revision : 8f231199a0a75788218320cdbcc7f70441e5d574
2006-05-23Code cleanup.Kevin Lim
cpu/base_dyn_inst.hh: Code cleanup --HG-- extra : convert_revision : 501c03f8e4346ffbcb545ddeee30c1f8ded9baa7
2006-05-23Move kernel stats out of CPU and into XC.Kevin Lim
arch/alpha/ev5.cc: Move kernel stats out of CPU and into XC. Also be sure to check if the kernel stats exist prior to using them. --HG-- extra : convert_revision : 565cd7026410fd7d8586f953d9b328c2e67a9473
2006-05-23Add extra flags to help new CPU handle various instructions.Kevin Lim
IsIprAccess flag may go away in the future (op class can be used to tell this), and the CPU still needs a specific way to identify/deal with syscalls. arch/alpha/isa/decoder.isa: Added a few extra flags to help the new CPU identify various classes of instructions without having to force certain behaviors for all CPUs. cpu/base_dyn_inst.hh: cpu/static_inst.hh: Added extra flags. cpu/o3/iew_impl.hh: cpu/o3/inst_queue_impl.hh: Handle store conditionals specially. cpu/o3/lsq_unit_impl.hh: Extra flags tells if the instruction is a store conditional. cpu/o3/rename_impl.hh: Handle IPR accesses and store conditionals specially. --HG-- extra : convert_revision : 39debec4fa5341ae8a8ab5650bd12730aeb6c04f
2006-05-22Undo changes to instruction flags that has caused statistics to change in ↵Kevin Lim
regressions. This temporarily will break the O3 and Ozone CPU models. Updates to fix them will be coming soon. arch/alpha/isa/decoder.isa: Undo changes to instruction flags that has caused statistics to change in regressions. --HG-- extra : convert_revision : c0fa9d55a22cae7c4f02d388870565b205d6fba3
2006-05-21Threads start off in suspended status now (Korey's changes for SMT).Kevin Lim
--HG-- extra : convert_revision : ad726f9f258e1983d2af5057ff6e5f9d2a5dd072
2006-05-19O3 code update/cleanup.Kevin Lim
cpu/o3/commit_impl.hh: O3 code update/cleanup. Fetch fault code no longer needed (see previous checkin). --HG-- extra : convert_revision : f602e7f978e19b8900dce482f38f9c7a195e94da
2006-05-19Remove sat_counter.cc and put its code into sat_counter.hh.Kevin Lim
cpu/SConscript: Remove sat_counter.cc and push its functions into the .hh file (all functions were 3 or less lines). cpu/o3/sat_counter.hh: Incorporate .cc code into this file. --HG-- extra : convert_revision : d75b1319292b00b00af1ce377cc0215fd06e6916
2006-05-19Rename function to be more expressive.Kevin Lim
--HG-- extra : convert_revision : 0c01b6d5309e2d09f03631740c9b0c8619ea26c4
2006-05-19IEW/IQ code cleanup and reorganization.Kevin Lim
Dependecy graph code moved into its own class. This requires the changes to the functional units, which is in the next check in. cpu/o3/iew.hh: cpu/o3/iew_impl.hh: IEW and IQ code cleanup and reorganization. cpu/o3/inst_queue.cc: Dependency graph code moved into its own class now. cpu/o3/inst_queue.hh: IEW/IQ code cleanup and reorganization. Dependecy graph code moved into its own class. cpu/o3/inst_queue_impl.hh: IEW/IQ code cleanup and reorganization. Dependecy graph code moved into its own class. Issue loop cleaned up, with completion events for functional units now used more correctly (before they weren't used for multi-cycle ops with pipelined FU's). --HG-- extra : convert_revision : 35e50192df6f71dc81d46a73fdd65f7ec07c10e4
2006-05-19Move activity tracking code into its own class. Now the CPU no longer has ↵Kevin Lim
to keep track of the activity tracking internals; it just calls advance() on the class and uses it to tell if it should deschedule itself. SConscript: Split off activity/idling code into its own class to do the processing separately. cpu/o3/alpha_cpu_builder.cc: cpu/o3/alpha_params.hh: Activity stuff. This is mostly for debugging and may be removed later on (or changed to enable/disable activity idling). cpu/o3/cpu.cc: Move activity idling stuff mostly into its own class, so it no longer clutters this file. cpu/o3/cpu.hh: Move activity idling stuff into its own class. python/m5/objects/AlphaFullCPU.py: Add parameter for initial activity value. --HG-- extra : convert_revision : f32f7cc03895dc07ab57ddba78c5402a1a8b0f1a
2006-05-19Fixes for regression build errors.Kevin Lim
--HG-- extra : convert_revision : 1f59c853cb0e327d7cf586021b5139f1242e4f28
2006-05-17Faults generated at fetch are passed to the backend by creating a dummy nop ↵Kevin Lim
instruction and giving it the fault. This unifies front end faults and normal instruction faults. cpu/checker/cpu.cc: Fixups for fetch fault being sent with the instruction. cpu/o3/fetch_impl.hh: cpu/ozone/front_end_impl.hh: Send any faults generated at fetch along with a fake nop instruction to the back end. This avoids having to use direct communication to check if the entire front end has drained; it is naturally handled through the nop's fault being handled when it reaches the head of commit. cpu/ozone/front_end.hh: Add extra status TrapPending. cpu/ozone/lw_back_end_impl.hh: Fetch fault handled through a dummy nop carrying the fetch fault. Avoid putting Nops on the exeList. --HG-- extra : convert_revision : 8d9899748b34c204763a49c48a9b5113864f5789
2006-05-17Backport ISA scanner fix from newmem to work withSteve Reinhardt
scons 0.96.9* versions. arch/SConscript: Backport ISA scanner fix from newmem. --HG-- extra : convert_revision : 96be75660f85900fd26badef36fb4109b36d8394
2006-05-16Merge ktlim@zamp:/z/ktlim2/clean/m5-o3Kevin Lim
into zamp.eecs.umich.edu:/z/ktlim2/clean/m5-merge --HG-- extra : convert_revision : 077a04edf0e3e4d735e88c9741d6742666e97de6
2006-05-16Update configuration files.Kevin Lim
--HG-- extra : convert_revision : f733bc68758d95987dfc481d48a4623c23b16ede
2006-05-16Merge ktlim@zizzer:/bk/m5Kevin Lim
into zamp.eecs.umich.edu:/z/ktlim2/clean/m5-merge --HG-- extra : convert_revision : 182df443376e5561d46f323d36089a2a49dc2024
2006-05-16Include checker and trap latency parameters.Kevin Lim
--HG-- extra : convert_revision : 148c59f430874e8425952db6960ca4f5e57e2a42
2006-05-16Sampler updates.Kevin Lim
cpu/ozone/cpu.hh: Updates for sampler. cpu/ozone/cpu_impl.hh: Updates for sampler, checker. cpu/ozone/inorder_back_end.hh: Sampler updates. Also support old memory system. --HG-- extra : convert_revision : 33ebe38e4c08d49c6af84032b819533b784b4fe8
2006-05-16Updates for sampler, checker, and general correctness.Kevin Lim
cpu/o3/alpha_cpu.hh: Update for sampler to work properly. Also code cleanup. cpu/o3/alpha_cpu_builder.cc: cpu/o3/alpha_dyn_inst.hh: Updates to support the checker. cpu/o3/alpha_cpu_impl.hh: Updates to support the checker. Also general code cleanup. cpu/o3/alpha_dyn_inst_impl.hh: Code cleanup. cpu/o3/alpha_params.hh: Updates to support the checker. Also supports trap latencies set through the parameters. cpu/o3/commit.hh: Supports sampler, checker. Code cleanup. cpu/o3/commit_impl.hh: Updates to support the sampler and checker, as well as general code cleanup. cpu/o3/cpu.cc: cpu/o3/cpu.hh: Support sampler and checker. cpu/o3/decode_impl.hh: Supports sampler. cpu/o3/fetch.hh: Supports sampler. Also update to hold the youngest valid SN fetch has seen to ensure that the entire pipeline has been drained. cpu/o3/fetch_impl.hh: Sampler updates. Also be sure to not fetches to uncached space (bad path). cpu/o3/iew.hh: cpu/o3/iew_impl.hh: Sampler updates. cpu/o3/lsq_unit_impl.hh: Supports checker. cpu/o3/regfile.hh: No need for accessing xcProxies directly. cpu/o3/rename.hh: cpu/o3/rename_impl.hh: Sampler support. --HG-- extra : convert_revision : 03881885dd50ebbca13ef31f31492fd4ef59121c
2006-05-16Add in checker. Supports dynamically verifying the execution of ↵Kevin Lim
instructions, as well as limited amount of control path verification. It will verify anything within the program, but anything external (traps, interrupts, XC) it assumes is redirected properly by the CPU. Similarly it assumes the results of store conditionals, uncached loads, and instructions marked as "unverifiable" are correct from the CPU. base/traceflags.py: build/SConstruct: cpu/SConscript: cpu/cpu_models.py: Add in Checker. cpu/base.cc: Add in checker support. Also XC status starts off as suspended. cpu/base.hh: Add in checker. --HG-- extra : convert_revision : 091b5cc83e837858adb681ef0137a0beb30bd1b2
2006-05-16Sampler updates.Kevin Lim
--HG-- extra : convert_revision : 9f88846d3e91ba725e1c2e0107568ba0f21f4638
2006-05-16Sampling fixes related to the quiesce event.Kevin Lim
cpu/cpu_exec_context.cc: cpu/cpu_exec_context.hh: Sampling fixes. The CPU models may switch during a quiesce period, so it needs to be sure to wake up the right XC. cpu/exec_context.hh: Return the EndQuiesceEvent specifically. sim/pseudo_inst.cc: Return the EndQuiesceEvent specifically for sampling. --HG-- extra : convert_revision : f9aa1fc8d4db8058f05319cb6a3d4605ce93b4c8
2006-05-16Add some flags for the upcoming checker.Kevin Lim
arch/alpha/isa/decoder.isa: Mark store conditionals as serializing. This is slightly higher over head than they truly have in the 264, but it's close. Normally they block any other instructions from entering the IQ until the IQ is empty. This is higher overhead because it waits until the ROB is empty. Also mark RPCC as unverifiable. The checker will just grab the value from the instruction and assume it's correct. cpu/static_inst.hh: Add unverifiable flag, specifically for the CheckerCPU. --HG-- extra : convert_revision : cbc34d1f2f5b07105d31d4bd8f19edae2cf8158e
2006-05-12replace /.automount/ with /n/Ali Saidi
--HG-- extra : convert_revision : 8b9ad49fa7e2e8863ebaf3f6709fc4fda62f2862
2006-05-12fix the checkpoint bugAli Saidi
--HG-- extra : convert_revision : 1ccae3282737d70b14ff86c8647e2e662a42c3bc
2006-05-11Fixes for ozone CPU to successfully boot and run linux.Kevin Lim
cpu/base_dyn_inst.hh: Remove snoop function (did not mean to commit it). cpu/ozone/back_end_impl.hh: Set instruction as having its result ready, not completed. cpu/ozone/cpu.hh: Fixes for store conditionals. Use an additional lock addr list to make sure that the access is valid. I don't know if this is fully necessary, but it gives me a peace of mind (at some performance cost). Make sure to schedule for cycles(1) and not just 1 cycle in the future as tick = 1ps. Also support the new Checker. cpu/ozone/cpu_builder.cc: Add parameter for maxOutstandingMemOps so it can be set through the config. Also add in the checker. Right now it's a BaseCPU simobject, but that may change in the future. cpu/ozone/cpu_impl.hh: Add support for the checker. For now there's a dynamic cast to convert the simobject passed back from the builder to the proper Checker type. It's ugly, but only happens at startup, and is probably a justified use of dynamic cast. Support switching out/taking over from other CPUs. Correct indexing problem for float registers. cpu/ozone/dyn_inst.hh: Add ability for instructions to wait on memory instructions in addition to source register instructions. This is needed for memory dependence predictors and memory barriers. cpu/ozone/dyn_inst_impl.hh: Support waiting on memory operations. Use "resultReady" to differentiate an instruction having its registers produced vs being totally completed. cpu/ozone/front_end.hh: Support switching out. Also record if an interrupt is pending. cpu/ozone/front_end_impl.hh: Support switching out. Also support stalling the front end if an interrupt is pending. cpu/ozone/lw_back_end.hh: Add checker in. Support switching out. Support memory barriers. cpu/ozone/lw_back_end_impl.hh: Lots of changes to get things to work right. Faults, traps, interrupts all wait until all stores have written back (important). Memory barriers are supported, as is the general ability for instructions to be dependent on other memory instructions. cpu/ozone/lw_lsq.hh: Support switching out. Also use store writeback events in all cases, not just dcache misses. cpu/ozone/lw_lsq_impl.hh: Support switching out. Also use store writeback events in all cases, not just dcache misses. Support the checker CPU. Marks instructions as completed once the functional access is done (which has to be done for the checker to be able to verify results). cpu/ozone/simple_params.hh: Add max outstanding mem ops parameter. python/m5/objects/OzoneCPU.py: Add max outstanding mem ops, checker. --HG-- extra : convert_revision : f4d408e1bb1f25836a097b6abe3856111e950c59
2006-05-11make the dma buffer equal to the max dma sizeAli Saidi
--HG-- extra : convert_revision : 87adee6c2239f67976675c9291dc4fbaa4f67507
2006-05-11ide printing to match newmemAli Saidi
--HG-- extra : convert_revision : ca6665bd93d257a8cf9d43600828ac22998c5810
2006-05-11make m5 panic a little more verboseAli Saidi
--HG-- extra : convert_revision : 32f52d829040c06c8a62cab1a7af1ed3b453b6f9
2006-05-11Small fixes to O3 model.Kevin Lim
cpu/o3/alpha_dyn_inst.hh: Set the instResult using a function on the base dyn inst. cpu/o3/bpred_unit_impl.hh: Don't need to reset the state. cpu/o3/commit_impl.hh: Mark instructions as completed. Wait until all stores are written back to handle a fault. cpu/o3/cpu.cc: Clear instruction lists when switching out. cpu/o3/lsq_unit.hh: Allow wbEvent to be set externally. cpu/o3/lsq_unit_impl.hh: Mark instructions as completed properly. Also use events for writing back stores even if there is a hit in the dcache. --HG-- extra : convert_revision : 172ad088b75ac31e848a5040633152b5c051444c
2006-05-11Set memory properly.Kevin Lim
--HG-- extra : convert_revision : 4e6c61d31bf052bb4aabf4bb7a4f0e870b44b771
2006-05-11Separate out result being ready and the instruction being complete.Kevin Lim
--HG-- extra : convert_revision : 9f17af114bf639f8fb61896e49fa714932c081d7
2006-05-04O3 CPU now handles being used with the sampler.Kevin Lim
cpu/o3/2bit_local_pred.cc: cpu/o3/2bit_local_pred.hh: cpu/o3/bpred_unit.hh: cpu/o3/bpred_unit_impl.hh: cpu/o3/btb.cc: cpu/o3/btb.hh: cpu/o3/commit.hh: cpu/o3/commit_impl.hh: cpu/o3/cpu.cc: cpu/o3/cpu.hh: cpu/o3/decode.hh: cpu/o3/decode_impl.hh: cpu/o3/fetch.hh: cpu/o3/fetch_impl.hh: cpu/o3/fu_pool.cc: cpu/o3/fu_pool.hh: cpu/o3/iew.hh: cpu/o3/iew_impl.hh: cpu/o3/inst_queue.hh: cpu/o3/inst_queue_impl.hh: cpu/o3/lsq.hh: cpu/o3/lsq_impl.hh: cpu/o3/lsq_unit.hh: cpu/o3/lsq_unit_impl.hh: cpu/o3/mem_dep_unit.hh: cpu/o3/mem_dep_unit_impl.hh: cpu/o3/ras.cc: cpu/o3/ras.hh: cpu/o3/rename.hh: cpu/o3/rename_impl.hh: cpu/o3/rob.hh: cpu/o3/rob_impl.hh: cpu/o3/sat_counter.cc: cpu/o3/sat_counter.hh: cpu/o3/thread_state.hh: Handle switching out and taking over. Needs to be able to reset all state. cpu/o3/alpha_cpu_impl.hh: Handle taking over from another XC. --HG-- extra : convert_revision : b936e826f0f8a18319bfa940ff35097b4192b449
2006-05-03Fixes for the sampler.Kevin Lim
cpu/simple/cpu.cc: Sampler fixes. The status may be switched out when calling activate or suspend if there is a switchover during a quiesce. --HG-- extra : convert_revision : da026e75dfb86289484cf01c5b1ecd9b03a72bd3
2006-05-03XC needs to get memory from the process.Kevin Lim
--HG-- extra : convert_revision : a2c014276824255a896a7e353f919fe81071091e
2006-05-02Fix some of lisa's barchart changesNathan Binkert
util/stats/barchart.py: - there is no self.inner_axes - don't append an empty value to self.xsubticks, otherwise subsequent calls will get extra empty ticks - rotate labels 30 degrees instead of 90 so it looks better --HG-- extra : convert_revision : 1cbac6d1f92bfc6b2c1e886ad5f9d4c78a2b3820
2006-04-26Major update to sinic to support VSINIC betterNathan Binkert
dev/sinic.cc: - Size the virtualRegs array based on the configured value - Add debugging stuff for uniquely identifying vnic usage - Only count totally unprocessed packets when notifying via RxDone - Add initial virtual address support - Fix some bugs in accessing packets out of order to make sure that busy packets are processed first - Add fifo watermark stuff - Make number of vnics, zero/delay copy and watermarks parameters dev/sinic.hh: add rxUnique and txUnique to uniquely identify tx and rx VNICs Create a separate list of Busy VNICs since more than one might be busy and we want to service those first Add more watermark stuff and new parameters dev/sinicreg.hh: Make the number of virtual nics a read-only parameter add bits for ZeroCopy/DelayCopy rename Virtual to Vaddr so it's not ambiguous Add a flag for TxData/RxData to indicate a virtual address Report rxfifo status in RxDone python/m5/objects/Ethernet.py: add more options for the fifo thresholds add number of vnics as a parameter add copy type as a parameter add virtual addressing as a parameter --HG-- extra : convert_revision : 850e2433b585d65469d4c5d85ad7ca820db10f4a
2006-04-26Bit of formatting for sinicreg.hhNathan Binkert
dev/sinicreg.hh: Formatting --HG-- extra : convert_revision : 267a63f866342b34d9be680d7aa54c2490fb8fd9
2006-04-25more debugging for sinicNathan Binkert
dev/sinic.cc: more debugging fix assert --HG-- extra : convert_revision : 11ac750080f1e65415ff3735011c0b830fbcf72f
2006-04-25more debugging for sinicNathan Binkert
dev/sinic.cc: better panic messages better debugging --HG-- extra : convert_revision : 06a9c6c8365ba1c1e58276ed63f299c6be25f0ba
2006-04-25Fix segfault in sinicNathan Binkert
dev/sinic.cc: check that there is a fault before testing the fault type --HG-- extra : convert_revision : 0cc95ba660655766b779e77d912dbc685cd476a8
2006-04-24Quiesce stuff.Kevin Lim
cpu/ozone/cpu.hh: Add quiesce stat (not clear how it should be used yet). cpu/ozone/cpu_impl.hh: Fix for quiesce. --HG-- extra : convert_revision : a1998818e241374ae3f4c3cabbef885dda55c884