Age | Commit message (Collapse) | Author |
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cpu/o3/2bit_local_pred.cc:
cpu/o3/2bit_local_pred.hh:
cpu/o3/bpred_unit.hh:
cpu/o3/bpred_unit_impl.hh:
cpu/o3/btb.cc:
cpu/o3/btb.hh:
cpu/o3/commit.hh:
cpu/o3/commit_impl.hh:
cpu/o3/cpu.cc:
cpu/o3/cpu.hh:
cpu/o3/decode.hh:
cpu/o3/decode_impl.hh:
cpu/o3/fetch.hh:
cpu/o3/fetch_impl.hh:
cpu/o3/fu_pool.cc:
cpu/o3/fu_pool.hh:
cpu/o3/iew.hh:
cpu/o3/iew_impl.hh:
cpu/o3/inst_queue.hh:
cpu/o3/inst_queue_impl.hh:
cpu/o3/lsq.hh:
cpu/o3/lsq_impl.hh:
cpu/o3/lsq_unit.hh:
cpu/o3/lsq_unit_impl.hh:
cpu/o3/mem_dep_unit.hh:
cpu/o3/mem_dep_unit_impl.hh:
cpu/o3/ras.cc:
cpu/o3/ras.hh:
cpu/o3/rename.hh:
cpu/o3/rename_impl.hh:
cpu/o3/rob.hh:
cpu/o3/rob_impl.hh:
cpu/o3/sat_counter.cc:
cpu/o3/sat_counter.hh:
cpu/o3/thread_state.hh:
Handle switching out and taking over. Needs to be able to reset all state.
cpu/o3/alpha_cpu_impl.hh:
Handle taking over from another XC.
--HG--
extra : convert_revision : b936e826f0f8a18319bfa940ff35097b4192b449
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cpu/simple/cpu.cc:
Sampler fixes. The status may be switched out when calling activate or suspend if there is a switchover during a quiesce.
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extra : convert_revision : da026e75dfb86289484cf01c5b1ecd9b03a72bd3
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--HG--
extra : convert_revision : a2c014276824255a896a7e353f919fe81071091e
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cpu/ozone/cpu.hh:
Add quiesce stat (not clear how it should be used yet).
cpu/ozone/cpu_impl.hh:
Fix for quiesce.
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extra : convert_revision : a1998818e241374ae3f4c3cabbef885dda55c884
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cpu/inst_seq.hh:
cpu/o3/cpu.cc:
cpu/ozone/cpu_builder.cc:
cpu/ozone/thread_state.hh:
SE build fixes.
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extra : convert_revision : a4df6128533105f849b5469f62d83dffe299b7df
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--HG--
extra : convert_revision : 72ddd75ad0b5783aca9484e7d178c2915ee8e355
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--HG--
extra : convert_revision : 7abb491e89e3e1a331cd19aa05ddce5184abf9e0
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cpu/o3/alpha_cpu.hh:
Store conditionals should not write their data to memory if they failed.
cpu/o3/lsq_unit.hh:
Setup request parameters when they're needed.
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extra : convert_revision : d75cd7deda03584b7e25cb567e4d79032cac7118
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--HG--
extra : convert_revision : a2422e30ace9874ba1be44cd0e1d3024cabbf1ed
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--HG--
extra : convert_revision : 669e4c32f2bc2c035a4199d6152a638b75a25148
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--HG--
extra : convert_revision : f8c8751aab62df5d57c6491c5ce9b90b5a176e86
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cpu/static_inst.hh:
Updates for new CPU, also include a classification of quiesce instructions.
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extra : convert_revision : a34cd56da88fe57d7de24674fbb375bbf13f887f
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cpu/exec_context.hh:
Remove functions that shouldn't be accessible to anything outside of the CPU.
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extra : convert_revision : 9793c3ceb6d5404484bafc7a75d75ed71815d9eb
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--HG--
extra : convert_revision : be899403d893f5ab6c11ae5a4334c0e36bd6ff61
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build/SConstruct:
Include Ozone CPU models.
cpu/cpu_models.py:
Include OzoneCPU models.
--HG--
extra : convert_revision : 51a016c216cacd2cc613eed79653026c2edda4b3
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arch/alpha/isa/decoder.isa:
Make IPR accessing instructions serializing so they are not issued incorrectly in the O3 model.
arch/alpha/isa/pal.isa:
Allow IPR instructions to have flags.
base/traceflags.py:
Include new trace flags from the two new CPU models.
cpu/SConscript:
Create the templates for the split mem accessor methods. Also include the new files from the new models (the Ozone model will be checked in next).
cpu/base_dyn_inst.cc:
cpu/base_dyn_inst.hh:
Update to the BaseDynInst for the new models.
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extra : convert_revision : cc82db9c72ec3e29cea4c3fdff74a3843e287a35
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base/timebuf.hh:
namespace fix.
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extra : convert_revision : 38e880b9394cf2923e2fb9775368cd93d719f950
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SConscript:
Move quiesce event to its own file/class.
--HG--
extra : convert_revision : 6aa7863adb529fc03142666213c3ec348825bd3b
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the fault is invoked.
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extra : convert_revision : b5f00fff277e863b3fe43422bc39d0487c482e60
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--HG--
extra : convert_revision : 321ff3c6e8dcc41f18e983fac83e14c037081dcb
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for prefetching with blocking buffers.
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extra : convert_revision : 7b401cf76742ffda6c911faf710970c58a0c337b
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--HG--
extra : convert_revision : 0f3a45745b0122de64a2f434604a474df04f2938
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--HG--
extra : convert_revision : 1019fd1e2bb484e1ea8f15db8dbe8e7a0201bd58
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discussion on setting paramaters.
SConscript:
Add support for detailed DRAM model
--HG--
extra : convert_revision : b65f9a810fa95957b585c85632ac20f9283337d1
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To run it use
-ETEST=POVRAY_BENCH to run the built in povray benchmark program (more CPU intensive, small fileset ~11MB)
-ETEST=POVRAY_AUTUMN to run the first part of a rendering of a autumn leaves/tree scene, less cpu intensive ~500MB working set.
For now I have been running with -ESYSTEM=Simple in order to drop checkpoints (built into binary at the point the render begins) and create memory traces.
I will check in a SYSTEM=3D_DRAM and SYSTEM=3D_CACHE configuration as soon as those are ready.
--HG--
extra : convert_revision : fb55834a02317d5e9961a5145c932965c8bc6a0e
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building.
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extra : convert_revision : 2c2562da323fa1249af72af3a89c7666c745ae2b
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into zazzer.eecs.umich.edu:/z/rdreslin/m5bk/m5
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extra : convert_revision : a4de274ec50821218121ba38f9215f2348262c27
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--HG--
extra : convert_revision : 357554632f102224357c8c3848bc4bc7cbb9dc54
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changed this in newmem.
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extra : convert_revision : 19b1ed0bb2c8bcde72843e62f73635e84adf95b5
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Add some forward declerations.
Fix ordering problem of variables in constructor (see sourceforge)
Factor out code from header into _impl file to speed building process (keep cache_builder smaller in size)
--HG--
extra : convert_revision : 20087f88f95628af716094e09c2287e09580149e
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an obsolete function that doesn't exist.
arch/alpha/tru64/process.cc:
sim/process.cc:
Don't include useless header.
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extra : convert_revision : 1dd5edeb0703e2190b89ea5ff563df4c95b7cf59
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--HG--
extra : convert_revision : c6d3a5af04731a92eaca2337424ba10926f0d879
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arch/alpha/isa_traits.hh:
arch/sparc/linux/process.cc:
fix merging problem
sim/syscall_emul.cc:
use setIntReg
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extra : convert_revision : e88d72e415493cd17d7b88c22c7e995f3199e396
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into zeep.eecs.umich.edu:/z/saidi/work/m5.ma2
arch/alpha/isa_traits.hh:
arch/alpha/linux/process.cc:
arch/sparc/isa_traits.hh:
arch/sparc/linux/process.cc:
sim/process.cc:
merge
--HG--
rename : cpu/exec_context.hh => cpu/cpu_exec_context.hh
extra : convert_revision : fea0155c8e23abbd0d5d5251abbd0f4d223fe935
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check abi-tag note section of elf binary for OS
add pseudo functions (moved from alpha and made to be generic)
move setsyscallreturn into isa traits
arch/alpha/SConscript:
no more common syscall emulation, now common for everyone
arch/alpha/isa_traits.hh:
move setsyscallreturn into isa description
arch/alpha/linux/process.cc:
arch/alpha/tru64/process.cc:
use generic functions rather than alpha specific ones
arch/sparc/isa_traits.hh:
have consts for generic pseudo syscalls
arch/sparc/linux/process.cc:
use generic functions
base/loader/elf_object.cc:
check abi-tag note section of elf binary for OS
cpu/exec_context.hh:
move syssyscallreturn into isa traits
sim/process.cc:
find call num with a more generic
sim/syscall_emul.cc:
sim/syscall_emul.hh:
add pseudo functions (moved from alpha and made to be generic)
--HG--
extra : convert_revision : 5a31024ecde7e39b830365ddd84593ea501a34d2
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into zizzer.eecs.umich.edu:/z/m5/Bitkeeper/multiarch
cpu/simple/cpu.cc:
Hand Merge
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rename : cpu/exec_context.hh => cpu/cpu_exec_context.hh
extra : convert_revision : bf664b092f993d0f4675ce8e7df13645a920c1f4
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cpu/exec_context.hh:
Include readNextNPC function.
cpu/simple/cpu.cc:
Use functions to set and access nextPC, nextNPC.
--HG--
extra : convert_revision : 22622b9c110e1d99cc9106a2a27c479579d7e1ad
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arch/alpha/isa_traits.hh:
arch/sparc/isa_traits.hh:
add nnpc for compiling purposes in exec_context setNextNPC function
cpu/exec_context.hh:
set NNPC function
cpu/simple/cpu.cc:
use NNPC in determining what PC we are using
--HG--
extra : convert_revision : e810cfbc5dc31879b20d2cc40bf9871613203532
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arch/mips/isa/decoder.isa:
comments
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extra : convert_revision : 8e4fdf36d7f7365cda062bc169a313bf860a4fe5
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into zazzer.eecs.umich.edu:/z/ksewell/research/m5-sim/multiarch-m5
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extra : convert_revision : f3502f293f6ea44b5cf209ce2a935a25bca6054f
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--HG--
extra : convert_revision : 41151d38cabb6ce0ea81e5d78e4474d8f2ffeb67
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arch/alpha/ev5.cc:
Include function for the MiscRegFile to copy all of the Iprs from an ExecContext.
arch/alpha/isa_traits.hh:
Include functions to copy MiscRegs from an ExecContext.
cpu/cpu_exec_context.cc:
Be sure to copy all of the misc regs when copying all architectural state.
--HG--
extra : convert_revision : cb948b5ff141ea0f739a1016f98236bd2a512f76
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into zamp.eecs.umich.edu:/z/ktlim2/m5-proxyxc
arch/alpha/ev5.cc:
cpu/o3/cpu.hh:
SCCS merged
--HG--
extra : convert_revision : 38889011ea02005c8fd3a7f3b0be3395223f6166
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My change to exec_context.hh probably affected these files to no longer have MemoryController forward declared through a long chain of includes. MemoryController should be forward declared where it is used anyways.
dev/alpha_console.hh:
dev/uart.hh:
dev/uart8250.hh:
Forward declaration of MemoryController.
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extra : convert_revision : afaac4014e0eb3b6d5d385cd4444b77511e03b51
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into ewok.(none):/home/gblack/m5/multiarch
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extra : convert_revision : 5fe5a3d70774d6420b890237d9be4a5d0f00d17e
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arch/alpha/isa_traits.hh:
Changed the enums to const ints, and got rid of a few unnecessary constants.
arch/sparc/isa_traits.hh:
Got rid of the enums, and added in some missing constants.
--HG--
extra : convert_revision : ee47890af9d8c67300b31d8e0dda1d580bd21479
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update miscReg file access
arch/mips/isa/decoder.isa:
arch/mips/isa_traits.cc:
update miscRegfile access
arch/mips/isa_traits.hh:
Update MiscReg enum and miscRegFile definition
--HG--
extra : convert_revision : 9b6b9343d674e1e38e25bb9a4ffe4325142e7424
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MIPS option except isa_traits.*
which I need to update the misc. regfile accesses
arch/mips/faults.cc:
arch/mips/faults.hh:
alpha to mips
arch/mips/isa/base.isa:
add includes
arch/mips/isa/bitfields.isa:
more bitfields
arch/mips/isa/decoder.isa:
lots o' lots o' lots o' changes!!!!
arch/mips/isa/formats.isa:
include cop0.isa
arch/mips/isa/formats/basic.isa:
fix faults
arch/mips/isa/formats/branch.isa:
arch/mips/isa/formats/fp.isa:
arch/mips/isa/formats/int.isa:
arch/mips/isa/formats/mem.isa:
arch/mips/isa/formats/noop.isa:
arch/mips/isa/formats/trap.isa:
arch/mips/isa/formats/unimp.isa:
arch/mips/isa/formats/unknown.isa:
arch/mips/isa/formats/util.isa:
arch/mips/isa/operands.isa:
arch/mips/isa_traits.cc:
arch/mips/linux_process.cc:
merge MIPS-specific comilable/buidable files code into multiarch
arch/mips/isa_traits.hh:
merge MIPS-specific comilable/buidable files code into multiarch... the miscRegs file accesses i have
need to be recoded and everything should build then ...
arch/mips/stacktrace.hh:
file copied over
--HG--
extra : convert_revision : 4a72e14fc5fb0a0d1f8b205dadbbf69636b7fb1f
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set.
--HG--
extra : convert_revision : 548822baafe73b8041b7030feb1c4550fb80292f
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--HG--
extra : convert_revision : 07f397742a026cb6320dc29722d1db21157f26fa
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