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2006-02-19Merge zizzer.eecs.umich.edu:/z/m5/Bitkeeper/m5Gabe Black
into zizzer.eecs.umich.edu:/z/m5/Bitkeeper/multiarch arch/alpha/faults.hh: ur Using cleaned up fault class deiffinitions --HG-- extra : convert_revision : a600950d539be2be73358f072aa5426456bf3d2d
2006-02-19Remade some changes which were undoneGabe Black
cpu/base.hh: cpu/static_inst.hh: Changed include of targetarch/isa_traits.hh back to arch/isa_traits.hh cpu/exec_context.hh: Changed Fault back to Fault * --HG-- extra : convert_revision : 410f2e2472f8aa5bf92619a5defdf85f689a5597
2006-02-19Merge gblack@m5.eecs.umich.edu:/bk/multiarchGabe Black
into ewok.(none):/home/gblack/m5/multiarch --HG-- extra : convert_revision : 090b30a7f70294e1aeb13ba0bc15da4061bdf348
2006-02-19Changes to untemplate StaticInst and StaticInstPtr, change the isa to a ↵Gabe Black
namespace instead of a class, an improvement to the architecture specific header file selection system, and fixed up a few include paths. arch/alpha/alpha_linux_process.cc: Added using directive for AlphaISA namespace arch/alpha/alpha_memory.hh: arch/alpha/isa/branch.isa: cpu/pc_event.hh: Added typedefs for Addr arch/alpha/alpha_tru64_process.cc: arch/alpha/arguments.cc: Added using directive for AlphaISA arch/alpha/ev5.hh: Added an include of arch/alpha/isa_traits.hh, and a using directive for the AlphaISA namespace. arch/alpha/faults.hh: Added a typedef for the Addr type, and changed the formatting of the faults slightly. arch/alpha/isa/main.isa: Untemplatized StaticInst, added a using for namespace AlphaISA to show up in decoder.cc and the exec.ccs, relocated makeNop to decoder.hh arch/alpha/isa/mem.isa: Untemplatized StaticInst and StaticInstPtr arch/alpha/isa/pal.isa: cpu/base_dyn_inst.cc: Untemplatized StaticInstPtr arch/alpha/isa_traits.hh: Changed variables to be externs instead of static since they are part of a namespace and not a class. arch/alpha/stacktrace.cc: Untemplatized StaticInstPtr, and added a using directive for AlphaISA. arch/alpha/stacktrace.hh: Added some typedefs for Addr and MachInst, and untemplatized StaticInstPtr arch/alpha/vtophys.cc: Added a using directive for AlphaISA arch/alpha/vtophys.hh: Added the AlphaISA namespace specifier where needed arch/isa_parser.py: Changed the placement of the definition of the decodeInst function to be outside the namespaceInst namespace. base/loader/object_file.hh: cpu/o3/bpred_unit.hh: Added a typedef for Addr base/loader/symtab.hh: Added a typedef for Addr, and added a TheISA to Addr in another typedef base/remote_gdb.cc: Added a using namespace TheISA, and untemplatized StaticInstPtr base/remote_gdb.hh: Added typedefs for Addr and MachInst cpu/base.cc: Added TheISA specifier to some variables exported from the isa. cpu/base.hh: Added a typedef for Addr, and TheISA to some variables from the ISA cpu/base_dyn_inst.hh: Untemplatized StaticInstPtr, and added TheISA specifier to some variables from the ISA. cpu/exec_context.hh: Added some typedefs for types from the isa, and added TheISA specifier to some variables from the isa cpu/exetrace.hh: Added typedefs for some types from the ISA, and untemplatized StaticInstPtr cpu/memtest/memtest.cc: cpu/o3/btb.cc: dev/baddev.cc: dev/ide_ctrl.cc: dev/ide_disk.cc: dev/isa_fake.cc: dev/ns_gige.cc: dev/pciconfigall.cc: dev/platform.cc: dev/sinic.cc: dev/uart8250.cc: kern/freebsd/freebsd_system.cc: kern/linux/linux_system.cc: kern/system_events.cc: kern/tru64/dump_mbuf.cc: kern/tru64/tru64_events.cc: sim/process.cc: sim/pseudo_inst.cc: sim/system.cc: Added using namespace TheISA cpu/memtest/memtest.hh: cpu/trace/opt_cpu.hh: cpu/trace/reader/itx_reader.hh: dev/ide_disk.hh: dev/pcidev.hh: dev/platform.hh: dev/tsunami.hh: sim/system.hh: sim/vptr.hh: Added typedef for Addr cpu/o3/2bit_local_pred.hh: Changed the include to use arch/isa_traits.hh instead of arch/alpha/isa_traits.hh. Added typedef for Addr cpu/o3/alpha_cpu.hh: Added typedefs for Addr and IntReg cpu/o3/alpha_cpu_impl.hh: Added this-> to setNextPC to fix a problem since it didn't depend on template parameters any more. Removed "typename" where it was no longer needed. cpu/o3/alpha_dyn_inst.hh: Cleaned up some typedefs, and untemplatized StaticInst cpu/o3/alpha_dyn_inst_impl.hh: untemplatized StaticInstPtr cpu/o3/alpha_impl.hh: Fixed up a typedef of MachInst cpu/o3/bpred_unit_impl.hh: Added a using TheISA::MachInst to a function cpu/o3/btb.hh: Changed an include from arch/alpha/isa_traits.hh to arch/isa_traits.hh, and added a typedef for Addr cpu/o3/commit.hh: Removed a typedef of Impl::ISA as ISA, since TheISA takes care of this now. cpu/o3/cpu.cc: Cleaned up namespace issues cpu/o3/cpu.hh: Cleaned up namespace usage cpu/o3/decode.hh: Removed typedef of ISA, and changed it to TheISA cpu/o3/fetch.hh: Fized up typedefs, and changed ISA to TheISA cpu/o3/free_list.hh: Changed include of arch/alpha/isa_traits.hh to arch/isa_traits.hh cpu/o3/iew.hh: Removed typedef of ISA cpu/o3/iew_impl.hh: Added TheISA namespace specifier to MachInst cpu/o3/ras.hh: Changed include from arch/alpha/isa_traits.hh to arch/isa_traits.hh, and added a typedef for Addr. cpu/o3/regfile.hh: Changed ISA to TheISA, and added some typedefs for Addr, IntReg, FloatReg, and MiscRegFile cpu/o3/rename.hh: Changed ISA to TheISA, and added a typedef for RegIndex cpu/o3/rename_map.hh: Added an include for arch/isa_traits.hh, and a typedef for RegIndex cpu/o3/rob.hh: Added a typedef for RegIndex cpu/o3/store_set.hh: cpu/o3/tournament_pred.hh: Changed an include of arch/alpha/isa_traits.hh to arch/isa_traits.hh, and added a typedef of Addr cpu/ozone/cpu.hh: Changed ISA into TheISA, and untemplatized StaticInst cpu/pc_event.cc: Added namespace specifier TheISA to Addr types cpu/profile.hh: kern/kernel_stats.hh: Added typedef for Addr, and untemplatized StaticInstPtr cpu/simple/cpu.cc: Changed using directive from LittleEndianGuest to AlphaISA, which will contain both namespaces. Added TheISA where needed, and untemplatized StaticInst cpu/simple/cpu.hh: Added a typedef for MachInst, and untemplatized StaticInst cpu/static_inst.cc: Untemplatized StaticInst cpu/static_inst.hh: Untemplatized StaticInst by using the TheISA namespace dev/alpha_console.cc: Added using namespace AlphaISA dev/simple_disk.hh: Added typedef for Addr and fixed up some formatting dev/sinicreg.hh: Added TheISA namespace specifier where needed dev/tsunami.cc: dev/tsunami_io.cc: dev/tsunami_pchip.cc: Added using namespace TheISA. It might be better for it to be AlphaISA dev/tsunami_cchip.cc: Added typedef for TheISA. It might be better for it to be AlphaISA kern/linux/aligned.hh: sim/pseudo_inst.hh: Added TheISA namespace specifier to Addr kern/linux/linux_threadinfo.hh: Added typedef for Addr, and TheISA namespace specifier to StackPointerReg kern/tru64/mbuf.hh: Added TheISA to Addr type in structs sim/process.hh: Added typedefs of Addr, RegFile, and MachInst sim/syscall_emul.cc: Added using namespace TheISA, and a cast of VMPageSize to the int type sim/syscall_emul.hh: Added typecast for Addr, and TheISA namespace specifier for where needed --HG-- extra : convert_revision : 91d4f6ca33a73b21c1f1771d74bfdea3b80eff45
2006-02-19Merge zizzer:/bk/m5Ali Saidi
into pb15.local:/Users/ali/work/m5.head --HG-- extra : convert_revision : 774e4afbb0f9c3ae62843138b6d7195ea184ff92
2006-02-19forgot a negative signAli Saidi
--HG-- extra : convert_revision : 9cdb00198979fca831d3e6840f9c534671ccead3
2006-02-18Move Linux/Tru64 architecture independent code into kern/*Ali Saidi
leaving dependent code making way for solaris linux syscall emu. SConscript: Add two new files for syscall emulation Add getDesc() function arch/alpha/alpha_linux_process.cc: arch/alpha/alpha_tru64_process.cc: move architecture independent code into kern/linux/linux.(hh|cc) arch/alpha/alpha_linux_process.hh: arch/alpha/alpha_tru64_process.hh: Add getDesc function kern/linux/linux.hh: move generi linux syscall emulation code into kern/linux kern/tru64/tru64.hh: move generi tru64 syscall emulation code into kern/tru64 sim/process.cc: sim/process.hh: Push the function determination and calling stuff down to LiveProcess and out of the Linux/Tru64 classes respectively sim/syscall_emul.cc: sim/syscall_emul.hh: fnctl implementation was identical in tru64 and linux so moved to generic --HG-- extra : convert_revision : 103293dbe6fe2f7892de4929d17dc085def77026
2006-02-18Support NNPC and branch instructions ... Outputs to decoder.cc correctlyKorey Sewell
Edits to the CPU model may still need to be made to handle branch likely insts... arch/isa_parser.py: add a NNPC operand ... arch/mips/isa/base.isa: change SPARC to MIPS arch/mips/isa/decoder.isa: typo < to >= arch/mips/isa/formats/basic.isa: spacing arch/mips/isa/formats/branch.isa: add code for branch instructions (still need adjustments for the branch likely) arch/mips/isa/operands.isa: support for NNPC and R31 arch/mips/isa_traits.hh: NNPC Addr variable --HG-- extra : convert_revision : df03d2a71c36dbc00270c2e3d7882b4f09ed97ad
2006-02-18Merge gblack@m5.eecs.umich.edu:/bk/multiarchGabe Black
into ewok.(none):/home/gblack/m5/multiarch --HG-- extra : convert_revision : 8b2759d670a6a60142be748817ccef736d61dabf
2006-02-18Changed the isa from a class to a namespace, untemplated StaticInst and ↵Gabe Black
StaticInstPtr, converted things to using TheISA, cleaned up some header file paths, and improved the system which pulls header files from the appropriate architecture. --HG-- extra : convert_revision : 5087333fbaf442efb4b55e70376244629fff507d
2006-02-18few changes for nate:Lisa Hsu
1) cosmetic - removing visibility of meta axes except for the tick labels. 2) unless subticklabels defined, don't do meta axes. (instead of assuming if you have 3D graph, do meta axes) --HG-- extra : convert_revision : 396011ffaa51ea4066b34257f6fd5b3faac9d242
2006-02-18remove print statementsLisa Hsu
--HG-- extra : convert_revision : abd635034424eeb9685aea777440a02887ce81a6
2006-02-18more changes for subtick labels.Lisa Hsu
util/stats/barchart.py: oop forgot this for 1D graph cases. util/stats/chart.py: need to add default param to chart. --HG-- extra : convert_revision : f4e6c6c614d584e7928ed905e97608716455ab6c
2006-02-18Merge zizzer:/bk/m5Lisa Hsu
into zed.eecs.umich.edu:/z/hsul/work/m5/clean --HG-- extra : convert_revision : 5f7c75eb3f82d9b04edc0efece3b054b5d0fe81f
2006-02-18Now you can have sublabels for every bar using the self.xsubticklabels ↵Lisa Hsu
parameter. --HG-- extra : convert_revision : a6bdf3a972e81c84947b7d6ae76f828494a125c8
2006-02-18changes from mergedmemKorey Sewell
arch/mips/isa/formats/branch.isa: add branch_likely member functions cpu/base.hh: cpu/exec_context.hh: cpu/static_inst.hh: change from mergedmem --HG-- extra : convert_revision : d6ad6943e2ef09eac91a466fc5c9bd8e66bf319a
2006-02-18use string name to figure out if we have a "AndLink" instructionKorey Sewell
arch/mips/isa/operands.isa: uq -> uw --HG-- extra : convert_revision : eeac6dba813de8174d080a5fa9b5a396b345113a
2006-02-18MIPS generates ISA code through scons '.../decoder.cc'!!!Korey Sewell
Now, must create g++ compilable code ... arch/mips/isa/decoder.isa: missing a '}' ... edited a few instruction decodings ... arch/mips/isa/formats.isa: rearranged #include arch/mips/isa/formats/branch.isa: add Branch Likely and Unconditional format arch/mips/isa/formats/int.isa: move OperateNopCheckDecode template to another file ... arch/mips/isa/formats/noop.isa: change Alpha to Mips in noop.isa --HG-- extra : convert_revision : 4bf955fa6dffbbc99fb95fee7878f691e3df5424
2006-02-17Get rid of deque (poor memory allocation), switch them over to lists.Kevin Lim
Beware that using size() on a list is a O(n) operation. dev/ns_gige.hh: Remove typedefs that (I assume) were copied over from etherdev.hh. They were unused in the ns_gige code. --HG-- extra : convert_revision : 577954ec26b899bd6329ce6a4aaa1d9b0ba4f34c
2006-02-16Remove fake fault.Kevin Lim
Switch fault pointers to const pointers to prevent them from accidentally being changed. Fix some coding style. arch/alpha/ev5.cc: cpu/o3/commit_impl.hh: kern/kernel_stats.hh: Remove fake fault. arch/alpha/faults.cc: Remove fake fault, fix to have normal m5 line length limit, and change pointers to be const pointers so that the default faults aren't changed accidentally. arch/alpha/faults.hh: Fix to have normal m5 line length limit, change pointers to const pointers. sim/faults.cc: sim/faults.hh: Remove fake fault, change pointers to const pointers. --HG-- extra : convert_revision : 01d4600e0d4bdc1d177b32edebc78f86a1bbfe2e
2006-02-16Merge ktlim@zizzer:/bk/m5Kevin Lim
into zamp.eecs.umich.edu:/z/ktlim2/clean/m5-new arch/alpha/isa/mem.isa: Hand merge. --HG-- extra : convert_revision : c557aa4c867d84ab01139e509ee9f2ed05dd8ea0
2006-02-16Fixes to handle generating the initiateAcc and completeAcc functions a ↵Kevin Lim
little more cleanly. arch/alpha/isa/mem.isa: Avoid explicitly declaring the Mem variable. Instead break up the code blocks used to generate the initiate and complete functions. The templates reflect which operands need to be declared for each function (src, dest, or both). Loads use both the EA code and mem acc code for the initiate, and memacc code and postacc code for the complete. Stores use both the EA code and mem acc code for the initiate, and only post acc code for the complete. arch/isa_parser.py: Remove hack for mem ops. --HG-- extra : convert_revision : a367797a2cb698762bfc27be1da00bcbe9367150
2006-02-16Get ISA parser to at least include all the ISA correctly ... crashes with ↵Korey Sewell
"None" error arch/mips/isa/decoder.isa: CondBranch format split up into Branch & BranchLikely formats arch/mips/isa/formats.isa: include util.isa arch/mips/isa/formats/branch.isa: erroneous 'e' at top of code arch/mips/isa/formats/util.isa: util.isa --HG-- extra : convert_revision : 4fc44a05e2838749e66cd70f210e8a718b34cbf3
2006-02-16Merge zizzer:/bk/multiarchKorey Sewell
into zazzer.eecs.umich.edu:/z/ksewell/research/m5-sim/m5-multiarch --HG-- extra : convert_revision : 17b164847aee7e21d15d1a9d99aae43f46906c28
2006-02-16file name changes ... minor ISA changesKorey Sewell
arch/mips/isa/base.isa: restoring base.isa file ... arch/mips/isa/formats/basic.isa: add c++ emacs header arch/mips/isa/formats/branch.isa: added branch likely format arch/mips/isa/formats/int.isa: small change to python code --HG-- extra : convert_revision : defd592abb1a724f5f88b19c197b858420e92d17
2006-02-16Some changes which weren't needed before doing a bk pull were needed ↵Gabe Black
afterwards, for some reason. arch/alpha/ev5.cc: Took out the unnecessary check for a null Fault pointer. arch/alpha/isa/mem.isa: Changed Fault to Fault *, and removed underscores from fault names. --HG-- extra : convert_revision : 367a58a375f911185ddcc5fc826034af96427461
2006-02-16Merge gblack@m5.eecs.umich.edu:/bk/multiarchGabe Black
into ewok.(none):/home/gblack/m5/multiarch --HG-- extra : convert_revision : d8626acb2686e123ad0bb6cf94e85c992657470d
2006-02-16Changed the fault enum into a class, and fixed everything up to work with ↵Gabe Black
it. Next, the faults need to be pulled out of all the other code so that they are only used to communicate between the CPU and the ISA. SConscript: The new faults.cc file in sim allocates the system wide faults. When these faults are generated through a function interface in the ISA, this file may go away. arch/alpha/alpha_memory.cc: Changed Fault to Fault * and took the underscores out of fault names. arch/alpha/alpha_memory.hh: Changed Fault to Fault *. Also, added an include for the alpha faults. arch/alpha/ev5.cc: Changed the fault_addr array into a fault_addr function. Once all of the faults can be expected to have the same type, fault_addr can go away completely and the info it provided will come from the fault itself. Also, Fault was changed to Fault *, and underscores were taken out of fault names. arch/alpha/isa/decoder.isa: Changed Fault to Fault * and took the underscores out fault names. arch/alpha/isa/fp.isa: Changed Fault to Fault *, and took the underscores out of fault names. arch/alpha/isa/main.isa: Changed Fault to Fault *, removed underscores from fault names, and made an include of the alpha faults show up in all the generated files. arch/alpha/isa/mem.isa: Changed Fault to Fault * and removed underscores from fault names. arch/alpha/isa/unimp.isa: arch/alpha/isa/unknown.isa: cpu/exec_context.hh: cpu/ozone/cpu.hh: cpu/simple/cpu.cc: dev/alpha_console.cc: dev/ide_ctrl.cc: dev/isa_fake.cc: dev/pciconfigall.cc: dev/pcidev.cc: dev/pcidev.hh: dev/tsunami_cchip.cc: dev/tsunami_io.cc: dev/tsunami_pchip.cc: Changed Fault to Fault *, and removed underscores from fault names. arch/alpha/isa_traits.hh: Changed the include of arch/alpha/faults.hh to sim/faults.hh, since the alpha faults weren't needed. cpu/base_dyn_inst.cc: Changed Fault to Fault *, and removed underscores from fault names. This file probably shouldn't use the Unimplemented Opcode fault. cpu/base_dyn_inst.hh: Changed Fault to Fault * and took the underscores out of the fault names. cpu/exec_context.cc: cpu/o3/alpha_dyn_inst.hh: cpu/o3/alpha_dyn_inst_impl.hh: cpu/o3/fetch.hh: dev/alpha_console.hh: dev/baddev.hh: dev/ide_ctrl.hh: dev/isa_fake.hh: dev/ns_gige.hh: dev/pciconfigall.hh: dev/sinic.hh: dev/tsunami_cchip.hh: dev/tsunami_io.hh: dev/tsunami_pchip.hh: dev/uart.hh: dev/uart8250.hh: Changed Fault to Fault *. cpu/o3/alpha_cpu.hh: Changed Fault to Fault *, removed underscores from fault names. cpu/o3/alpha_cpu_impl.hh: Changed Fault to Fault *, removed underscores from fault names, and changed the fault_addr array to the fault_addr function. Once all faults are from the ISA, this function will probably go away. cpu/o3/commit_impl.hh: cpu/o3/fetch_impl.hh: dev/baddev.cc: Changed Fault to Fault *, and removed underscores from the fault names. cpu/o3/regfile.hh: Added an include for the alpha specific faults which will hopefully go away once the ipr stuff is moved, changed Fault to Fault *, and removed the underscores from fault names. cpu/simple/cpu.hh: Changed Fault to Fault * dev/ns_gige.cc: Changed Fault to Fault *, and removdd underscores from fault names. dev/sinic.cc: Changed Fault to Fault *, and removed the underscores from fault names. dev/uart8250.cc: Chanted Fault to Fault *, and removed underscores from fault names. kern/kernel_stats.cc: Removed underscores from fault names, and from NumFaults. kern/kernel_stats.hh: Changed the predeclaration of Fault from an enum to a class, and changd the "fault" function to work with the classes instead of the enum. Once there are no system wide faults anymore, this code will simplify back to something like it was originally. sim/faults.cc: This allocates the system wide faults. sim/faults.hh: This declares the system wide faults. sim/syscall_emul.cc: sim/syscall_emul.hh: Removed the underscores from fault names. --HG-- rename : arch/alpha/faults.cc => sim/faults.cc rename : arch/alpha/faults.hh => sim/faults.hh extra : convert_revision : 253d39258237333ae8ec4d8047367cb3ea68569d
2006-02-15Merge zizzer.eecs.umich.edu:/z/m5/Bitkeeper/m5Gabe Black
into zizzer.eecs.umich.edu:/z/m5/Bitkeeper/multiarch --HG-- extra : convert_revision : b4bbf63ec3b1c6de0ea7220e6dda5366c0529c07
2006-02-15...Korey Sewell
arch/mips/isa/base.isa: restore base.isa --HG-- extra : convert_revision : a551caae28f505b22bceae3297fc00b0fb6a0e23
2006-02-15Gives separate methods for initiating and completing a memory access, which ↵Kevin Lim
will be helpful for the merged memory model. arch/alpha/isa/mem.isa: Include methods that allow a memory operation to be split between the part that initiates the access, and the part that completes the access. In these functions the Mem variable is explicitly declared; in the default execute functions, the Mem variable is still handled through %(op_decl)s. arch/isa_parser.py: Include recording the type of the memory access variable so that it can be used if it needs to be explicitly declared in a template. Have memory operands consider themselves neither a source nor a destination to avoid including themselves on the op_src_decl list or the op_dest_decl list. Record op_src_decl and op_dest_decl lists to allow for declaring only source or destination operands. This is needed for the split memory access methods. --HG-- extra : convert_revision : f674f7a2f747ae40ba8c3a0933b0337c87ee0b6c
2006-02-15Merge zizzer:/bk/m5Ali Saidi
into pb15.local:/Users/ali/work/m5.head sim/byteswap.hh: SCCS merged --HG-- extra : convert_revision : 65989fef265ddfafb59a6c96e3cdde76eb3e071d
2006-02-15endian fixes and compiles on mac os xAli Saidi
arch/alpha/alpha_linux_process.cc: add endian conversions for fstat functions arch/alpha/alpha_tru64_process.cc: add endian conversions for various functions sim/byteswap.hh: for some reason gcc on macos really wants long and unsigned long Why int32_t and uint32_t isn't sufficient I don't know. sim/process.cc: sim/syscall_emul.hh: endian fixes --HG-- extra : convert_revision : ce625d5660b70867c43c74fbed856149c0d8cd36
2006-02-14Merge zizzer:/bk/multiarchKorey Sewell
into zazzer.eecs.umich.edu:/z/ksewell/research/m5-sim/m5-multiarch --HG-- extra : convert_revision : 5b0a3dd1a52ca9b29ea4a1c505a7435bfd6110fe
2006-02-14another big step to a parsable ISA ... no errors after I used a symbolic ↵Korey Sewell
link for arch/alpha/main.isa to test my files ... arch/mips/isa/operands.isa: use sd and ud instead of sdw and udw --HG-- extra : convert_revision : d66f3fd2c4a4d70e6015f0f1643c400cdfe73055
2006-02-14trying to get ISA to parse correctly ...Korey Sewell
arch/mips/isa/formats/unimp.isa: holds unimplemented formats arch/mips/isa/formats/unknown.isa: holds unknown formats --HG-- extra : convert_revision : 0f3a8ea7e3a1592322cce54527d6989152e57975
2006-02-14New files to fix building the SPARC_SE and MIPS_SE isa_parser.py generated ↵Gabe Black
files. --HG-- extra : convert_revision : 94a9543376f8b4709a4aef54c5ac0d6f582a9dad
2006-02-14Fixed a path in the alpha isa description.Gabe Black
--HG-- extra : convert_revision : 2a73ef7703ffe5c5232619698a16c8b4ee265a21
2006-02-14Merge zizzer:/bk/multiarchKorey Sewell
into zazzer.eecs.umich.edu:/z/ksewell/research/m5-sim/m5-multiarch --HG-- extra : convert_revision : 62d9346c44d5b7d455414fbebf0da3a8ef8d0754
2006-02-14make MIPS MT instructions decodable ...Korey Sewell
arch/mips/isa/bitfields.isa: extra bitfield for decoding --HG-- extra : convert_revision : 27f0afc3ee6ce00a94f44b2b1ac160ec26030866
2006-02-12Pseudo instructions are now passed whatever instructions they need by the ↵Gabe Black
decoder, rather than extracting them explicitly. This lets most of the pseudo instruction code to be shared across architectures. SConscript: Moved pseudo_inst.hh from targetarch to full system sources arch/alpha/SConscript: Moved pseudo_inst.cc out of the alpha specific sources arch/alpha/isa/decoder.isa: The decoder now pulls out the arguments for the pseudo instructions based on the alpha ABI arch/alpha/isa/main.isa: Registers 16, 17 and 18 are used to get parameters for the pseudo instructions and can be referred to explicitly sim/pseudo_inst.cc: Changed some include paths to reflect that pseudo_inst.hh is now outside of the alpha directory. Also, instead of extracting their parameters directly, they're passed in as regular function arguments. sim/pseudo_inst.hh: Changed the function prototypes to include the functions parameters, now that they aren't extracted from the execution context. --HG-- rename : arch/alpha/pseudo_inst.cc => sim/pseudo_inst.cc rename : arch/alpha/pseudo_inst.hh => sim/pseudo_inst.hh extra : convert_revision : 76ce768cf1d8a838aa7b64878a7ab4c4215ac999
2006-02-12Removed isa_traits.hh from targetarch, moved vptr.hh from arch/alpha to sim, ↵Gabe Black
fixed an include to have the new location, and removed an ambiguating function declaration in byteswap.hh. SConscript: Moved isa_fullsys_traits.hh out of targetarch, since the only place it's included, and the only place the comments in the file say it should be included, is in the alpha isa_traits.hh targetarch/isa_traits.hh is now included through arch/isa_traits.hh vptr.hh was removed from targetarch, and moved to sim arch/alpha/pseudo_inst.cc: Moved vptr.hh from targetarch to sim base/loader/object_file.hh: base/loader/symtab.hh: cpu/base.hh: dev/ide_disk.cc: Changed the include of isa_traits.hh from targetarch to arch cpu/static_inst.hh: dev/platform.hh: dev/simple_disk.hh: kern/tru64/dump_mbuf.cc: kern/tru64/mbuf.hh: kern/tru64/tru64_events.cc: kern/tru64/tru64_system.cc: kern/tru64/tru64_system.hh: sim/process.hh: sim/syscall_emul.hh: Changed the include of isa_traits.hh from targetarch to arch. kern/linux/linux_threadinfo.hh: Changed the include of vptr.hh from targetarch to sim. sim/byteswap.hh: Removed the line declaring swap_byte(long), since it ambiguates with swap_byte(int32_t) sim/vptr.hh: Fixed the assert in the equals operator. Changed the AlphaISA namespace reference to TheISA. Changed arch/alpha/vtophys.hh to targetarch/vtophys.hh, since this file is now for all architectures. Added an include of arch/isa_traits.hh so that TheISA would be defined. --HG-- extra : convert_revision : e3c6ac17ed0277cfeba1d35cd63eba66eba5996f
2006-02-12Merge gblack@m5.eecs.umich.edu:/bk/multiarchGabe Black
into ewok.(none):/home/gblack/m5/multiarch --HG-- extra : convert_revision : baf9b0eb84df7da8152ddf9a25264e041a24b8ca
2006-02-12vptr.hh:Gabe Black
Rename: arch/alpha/vptr.hh -> sim/vptr.hh --HG-- rename : arch/alpha/vptr.hh => sim/vptr.hh extra : convert_revision : 345745efec49f6169d1d9f61fd590240a995373b
2006-02-12Merge zizzer.eecs.umich.edu:/z/m5/Bitkeeper/m5Gabe Black
into zizzer.eecs.umich.edu:/z/m5/Bitkeeper/multiarch --HG-- extra : convert_revision : 427b5c957f91e66271444acebc01e1a861790363
2006-02-12Polishing of isa_parser.py internal operand handling, resulting inSteve Reinhardt
minor change to syntax of 'def operands' in ISA descriptions. arch/alpha/isa/main.isa: arch/mips/isa/operands.isa: arch/sparc/isa/operands.isa: Change 'def operands' statement to work with new isa_parser changes. arch/isa_parser.py: Merge OperandTraits and OperandDescriptor objects into a unified hierarchy of Operand objects. Required a change in the syntax of the 'def operands' statement in the ISA description. --HG-- extra : convert_revision : cb43f1607311497ead88ba13953d410ab5bc6a37
2006-02-11Minor cleanup of operand type and traits code in isa_parser.py.Steve Reinhardt
arch/isa_parser.py: Minor cleanup of operand type and traits code: - build operand size map right away when types are defined instead of waiting to do it lazily - check that operand types have been defined before operands - don't use 'type' as a variable name - use isinstance() instead of checking for types directly --HG-- extra : convert_revision : 099c1ee8d490f9c38316749bf87209388c55c971
2006-02-11Add keyword parameters and list-valued arguments toSteve Reinhardt
instruction format functions in ISA description language. Take advantage of these features to clean up memory instruction definitions in Alpha. arch/alpha/isa/decoder.isa: arch/alpha/isa/mem.isa: arch/alpha/isa/pal.isa: Take advantage of new keyword parameters to disambiguate instruction vs. memory-request flags, and to provide a default EA calculation for memory ops (since 99% of them are the same). arch/isa_parser.py: Add two new features to instruction format functions: - Keyword parameters, a la Python. - List-valued arguments. Also export makeList() function to Python code blocks, as this is handy for dealing with flags. --HG-- extra : convert_revision : 99bbbaa2e765230aa96b6a06ed193793325f9fb0
2006-02-11fix #if. I wonder why my compiler had no issues. Even though it is clearlyAli Saidi
wrong arch/alpha/alpha_linux_process.cc: fix #if. I wonder why my compiler had no issues --HG-- extra : convert_revision : 880a0442b28811db5ec548ce940060d4b26ec634
2006-02-11hello world works on a BE host for a LE guestAli Saidi
arch/alpha/alpha_linux_process.cc: Add endian conversions to fstat sim/byteswap.hh: for some reason I don't understand g++ really wanted a long version defined even though int32_t should be the same. --HG-- extra : convert_revision : 5bfe9d3f0b31824fa5a7ae3f51fd0be5ed4d555d