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2018-11-05systemc: Explicitly keep the sc_port bind alongside sc_in's version.Gabe Black
The sc_in bind function was hiding the one from sc_port by changing the const-ness of its parameter. This change explicitly exposes the underlying sc_port version, and keeps it alongside the new sc_in version. This seems mildly dangerous and undesirable because now there are two very similar functions which would both need to be overridden in order to get new behavior, but I don't think it's any more dangerous and undesirable than as (perhaps unintentionally) specified in the standard. Change-Id: Ib42a1f8e70bc97abeeeb8d614e71c4019b3a2323 Reviewed-on: https://gem5-review.googlesource.com/c/13880 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com>
2018-11-05systemc: Change how SC_BIND_PROXY_NIL is initialized.Gabe Black
The previous implementation dereferenced a null pointer to create a reference which would then have its address taken in the sc_bind_proxy constructor. clang says that that uses undefined behavior, so this change adds a default constructor which initializes the two contained pointers to null explicitly. We have to hope systemc code doesn't play around with sc_bind_proxy too much and doesn't accidentally use this constructor unintentionally, but it seems like the least bad possible solution which makes clang happy. Change-Id: Ic59603495fe7a406586a18ce44de979f84089bcd Reviewed-on: https://gem5-review.googlesource.com/c/13879 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com>
2018-11-05systemc: Get rid of implementations for some disabled sc_vector methods.Gabe Black
These don't need to exist, and the specifics of their stub implementations were upsetting clang. Change-Id: Ib38a39c5cfbc2e1647cfb6ed14c660e10df2b1c3 Reviewed-on: https://gem5-review.googlesource.com/c/13878 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com>
2018-11-05systemc: Move a function after the class it uses internally.Gabe Black
The class was defined, but only later in the file. By putting the function definition later, clang stops reporting an error. Change-Id: Id4dd1ec3f3a06f4d1dc10ef4ff8c545d98a6ae12 Reviewed-on: https://gem5-review.googlesource.com/c/13877 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com>
2018-11-05systemc: Get rid of an unused private member in sc_clock.Gabe Black
It's not useful, and having it makes clang upset. Change-Id: I51366fd18a287e186c88f08af5c6ba8692779003 Reviewed-on: https://gem5-review.googlesource.com/c/13876 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com>
2018-11-05mem-cache: Rename the tag class init function to tagsInit.Gabe Black
Since the tag classes are subclasses of SimObject, they inherit an init function which does generic initialization at simulation startup and which doesn't take any parameters. A new function was added which does take a parameter, and which is just for doing tag specific initialization as triggered by the base cache. These two names clashed, and clang complained that the tag local name was hiding the SimObject name (which it was). Change-Id: I399775aceaf8f1a8e2646d434facef22e6d3e7d0 Reviewed-on: https://gem5-review.googlesource.com/c/13875 Reviewed-by: Gabe Black <gabeblack@google.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Gabe Black <gabeblack@google.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2018-11-05mem: Use Packet writing functions instead of memcpyDaniel R. Carvalho
Classes were using memcpy instead of the Packet functions created for writing to/from the packet. This allows these writes to be better checked and tracked. This also fixes a bug in MemCheckerMonitor, which was using the incorrect type for the packet pointer. Change-Id: I5bbc8a24e59464e8219bb6d54af8209e6d4ee1af Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br> Reviewed-on: https://gem5-review.googlesource.com/c/13695 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2018-11-05mem-cache: Fix double block invalidationDaniel R. Carvalho
Block was being invalidated twice when not a tempBlock. Make explicit that the else case is only to be applied when handling the tempBlock, as otherwise the Tags should be taking care of the invalidation. Change-Id: Ie7603fdbe156c54e94bbdc83541b55e66f8d250f Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br> Reviewed-on: https://gem5-review.googlesource.com/c/13895 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2018-11-05arch, arm: Return s1Req upon fault in s2LookupAnouk Van Laer
When a s2Lookup object is created, a new request is created, based upon the original, stage 1 request sent out by the CPU. When a fault occurs during the second stage of translation, this new request is returned. This can lead to issues with the O3 CPU. The O3 fetch stage will not acknowledge the fault as it is a different request than the one it sent out and does not contain a contextID. This commit rectifies this. Change-Id: I21cb7377a59aed9d90d99f048b2106eaf219e93a Reviewed-by: Ciro Santilli <ciro.santilli@arm.com> Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/13782 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-11-05arch, arm: Effect of AT instructions on descriptor handlingAnouk Van Laer
Some address translation instructions will stop translation after the 1st stage and intercept the IPA, even in the presence of stage 2 (eg AT S1E1). However, in the case of a TLB miss, the table descriptors still need to be translated from IPA to PA to avoid fetching the wrong addresses. This commit splits whether IPA->PA translation is required for the VA and/or for the table descriptors. Change-Id: Ie53cdc00585f116150256f1d833460931b3bfb7d Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/13781 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-11-02util: Add some examples for using systemc code within gem5.Gabe Black
These examples have comments inside them that explain what they do. There's also a README file which explains how to use the examples generally, and at a high level what each one does. Change-Id: I223963dc1c190289986b2ee5705910dbcad4a4c9 Reviewed-on: https://gem5-review.googlesource.com/c/13376 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com>
2018-11-02util: Move the existing systemc example into a subdirectory.Gabe Black
This example is for how to embed gem5 within systemc and make it use the systemc event queue. This used to be the only method of using gem5 and systemc together, but now that there are other options, it's ambiguous to have it as the only thing in the util/systemc directory. This change moves it into a gem5_within_systemc subdirectory which clearly shows what type of integration that example corresponds with. Change-Id: I426d68ccb618397d820bef492cbb1ff8ef4a979b Reviewed-on: https://gem5-review.googlesource.com/c/13375 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com>
2018-10-30syscall_emul: fix openat when directory does not end in "/"Ciro Santilli
Before this commit, the following code: dir_fd = open(".", O_DIRECTORY); file_fd = openat(dir_fd, "ble", O_CREAT, S_IRUSR | S_IWUSR); would create a file called ".ble" in the current working directory, instead of the correct "ble". Change-Id: I1525a088d49744e29b760387afabef9f1ac98646 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/13005 Reviewed-by: Brandon Potter <Brandon.Potter@amd.com> Maintainer: Brandon Potter <Brandon.Potter@amd.com>
2018-10-29syscall_emul: implement arm openatCiro Santilli
This is especially important because the Ubuntu 18.04 packaged arm-linux-gnueabihf-gcc uses the system call on the program initialization, which leads all programs to fail with: fatal: syscall openat (#322) unimplemented. Change-Id: I5596162ad19644df7b6d21f2a46acc07030001ae Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/13004 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-10-29arch-arm: FIXUP for the add PRFM PST instruction commitYuetsu Kodama
Change-Id: I898e5b565c6591f88ae732b24713aeae2c827cbd Reviewed-on: https://gem5-review.googlesource.com/c/13815 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-10-26mem-ruby: Fix MOESI_CMP_directory in ports orderNikos Nikoleris
To avoid deadlocks ruby objects typically prioritize the handling of responses to all other events. The order in which in_port statements are written determine the order in which they are handled. This patch fixes the order of in_order statements for the L2 cache in the MOESI_CMP_directory. Change-Id: I62248b0480a88ac2cd945425155f0961a1cf6cb1 Signed-off-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/13595 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2018-10-26arch-arm: We add PRFM PST instruction for armyuetsu.kodama
Note current PRFM supports only PLD, but PST (prefetch for store) is also important for latency hiding. We also bug fix in disassembler to display prfop correctly. Change-Id: I9144e7233900aa2d555e1c1a6a2c2e41d837aa13 Signed-off-by: Yuetsu Kodama <yuetsu.kodama@riken.jp> Reviewed-on: https://gem5-review.googlesource.com/c/13675 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-10-26arch-arm: IMPDEF for SYS instruction with CRn = {11, 15}Giacomo Travaglini
According to the arm arm, a SYS instruction (op0 = 1) with CRn = (11 or 15) is implementation defined; this makes it trappable by having HCR_EL2.TIDCP = 1. Change-Id: Idd94ac345fee652ee6f8c0a7eb7b06ac75ec38ef Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/13780 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-10-26arch-arm: AArch64 Instruction for MISCREG_IMPDEF_UNIMPLGiacomo Travaglini
While there is a AArch32 class for instructions accessing implementation defined registers, we are lacking for the AArch64 counterpart. we were relying on FailUnimplemented, which is untrappable at EL2 (except for HCR_EL2.TGE) since it is just raising Undefined Instruction. Change-Id: I923cb914658ca958af031612cf005159707b0b4f Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/13779 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-10-26arch-arm: Refactor AArch64 MSR/MRS trappingGiacomo Travaglini
This patch refactors AArch64 MSR/MRS trapping, by moving the trapping helpers in arch/arm/utility and in the isa code into a MiscRegOp64 class. This class is the Base class for a generic AArch64 instruction which is making use of system registers (MiscReg), like MSR,MRS,SYS. The common denominator or those instruction is the chance that the system register access is trapped to an upper Exception level. MiscRegOp64 is providing that feature. What do we gain? Other "pseudo" instructions, like access to implementation defined registers can inherit from this class to make use of the trapping functionalities even if there is no data movement between GPRs and system register. Change-Id: I0924354db100de04f1079a1ab43d4fd32039e08d Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/13778 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-10-26arch-arm: Trap to EL2 only if not in Secure StateGiacomo Travaglini
MRS/MSR Instructions should trap to EL2 only if we are in non-Secure state since at the current implementation (Armv8.0) there is no Secure EL2. Change-Id: I93af415fbcbd19a470752adf6afc92e520e9645d Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/13777 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-10-26arch-arm: Fix HVC trapping beahviourGiacomo Travaglini
This patch is fixing HVC trapping behaviour, reusing the pseudocode implementation provided in the arm arm. Change-Id: I0bc81478400b99d84534c1c8871f894722f547c5 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/13776 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-10-26arch-arm: CPTR_EL3.TCPAC traps EL2 accesses to CPACR_EL1Giacomo Travaglini
According to the arm arm, CPTR_EL3.TCPAC traps EL2 accesses to the CPTR_EL2 or HCPTR, and EL2 and EL1 accesses to the CPACR_EL1 or CPACR, are trapped to EL3, unless they are trapped by CPTR_EL2.TCPAC. Change-Id: I637be35b29db39f044dda0c6cc4fe986c9620371 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/13775 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-10-26tests: Convert AddrRangeMap unit test to a GTestAndreas Sandberg
Change-Id: Ifeb0b57c0cda77706691286f78325e50edb31c0d Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/13736 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
2018-10-26tests: Convert CircleBuf unit test to a GTestAndreas Sandberg
Change-Id: I028c6b8d8e0ec06cac3d636689ae647f717096cd Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/13735 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
2018-10-22mem-cache: Move evictBlock(CacheBlk*, PacketList&) to baseDaniel R. Carvalho
Move evictBlock(CacheBlk*, PacketList&) to base cache, as it is both sub-classes implementations are equal. Change-Id: I80fbd16813bfcc4938fb01ed76abe29b3f8b3018 Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br> Reviewed-on: https://gem5-review.googlesource.com/c/13656 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2018-10-19config: add --param to fs.py, se.py and fs_bigLITTLE.pyCiro Santilli
The option allows to set SimObject params from the CLI. The existing config scripts have a large number of options that simply set a single SimObject parameter, and many still are not exposed. This commit allows users to pass arbitrary parameters from the command line to prevent the need for this kind of trivial option. Change-Id: Ic4bd36948aca4998d2eaf6369c85d3668efa3944 Reviewed-on: https://gem5-review.googlesource.com/c/12985 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2018-10-19python: Add utility function to override config parametersCiro Santilli
Add a utility method, SimObject.apply_config that can be used to implement SimObject param overrides from the command line. This function provides safe and convenient semantics for CLI assignment: * The override expression is evaluated in a restricted environment. The only global variables are the child objects and params from the root object. * Only params can be overridden. For example, calling methods or setting attributes on SimObjects isn't possible. * Vectors use non-standard list semantics which enable something similar to glob expansion on the shell. For example, setting: root.system.cpu[0:2].numThreads = 2 will override numThreads for cpu 0 and 1 and: root.system.cpus[0,2].numThreads = 2 sets it for cpus 0 and 2. The intention is that the helper method is called to override default values before calling m5.instantiate. Change-Id: I73f99da21d6d8ce1ff2ec8db2bb34338456f6799 Reviewed-on: https://gem5-review.googlesource.com/c/12984 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2018-10-19arm: treat aarch64 hints as NOPs instead of panicCiro Santilli
Change-Id: Ida2a746e6188171bd2e4da92a4efb33fcbaa2b69 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/13476 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-10-19arm: update hint instruction decoding to match ARMv8.5Ciro Santilli
This fixes: - unallocated hints that have since been allocated - unallocated and unimplemented hint instructions being treated as Unknown instead of the correct NOP - missing encoding for DBG on A32 Unallocated and unimplemented hints give a warning if executed. The most important fix was for the CSDB Spectre mitigation instruction, which was added recently and previously unallocated and treated as Unknown. The Linux kernel v4.18 ARMv7 uses CSDB it and boot would fail with "undefined instruction" since Linux commit 1d4238c56f9816ce0f9c8dbe42d7f2ad81cb6613 Change-Id: I283da3f08a9af4148edc6fb3ca2930cbb97126b8 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/13475 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-10-18mem-cache: Fix unused variable warning in FALRU:invalidate()Nikos Nikoleris
Change-Id: I3b902045433ca56b3e62c251158e784b5fa9e4d7 Signed-off-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/13600 Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
2018-10-18mem: Add write coalescing and write-no-allocate to the cachesNikos Nikoleris
Enable the cache to detect contiguous writes and hold on to the MSHR long enough to allow the entire line to be written. If the whole line is written, the MSHR will be sent out as an invalidation requests, as it is part of a whole-line write, i.e. no-fetch-on-write. The cache is also able to switch to a write-no-allocate policy on the actual completion of the writes, and instead use the tempBlock and turn the write operation into a writeback. These policies are all well-known, and described in works such as Jouppi, Cache Write Policies and Performance, vol 21, no 2, ACM, 1993. Change-Id: I19792f2970b3c6798c9b2b493acdd156897284ae Reviewed-on: https://gem5-review.googlesource.com/c/12907 Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2018-10-18mem: Delay servicing an MSHR after its allocationNikos Nikoleris
An MSHR is allocated and the computed latency determines when the MSHR will be ready and can be serviced by the cache. This patch adds a function that allows changing the time that an MSHR is ready and adjusts the queue such that other MSHRs can be serviced first if they are ready. Change-Id: Ie908191fcb3c2d84d4c6f855c8b1e41ca5881bff Reviewed-on: https://gem5-review.googlesource.com/c/12906 Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2018-10-18mem: Restructure whole-line writes to simplify write mergingNikos Nikoleris
This patch changes how we deal with whole-line writes their responses. With these changes, we use the MSHR tracking to determine if a whole-line is written, and on a fill we simply handle the invalidation response, with the actual writes taking place as part of satisfying the CPU-side hit. Change-Id: I9a18e41a95db3c20b97f8bca7d95ff33d35a578b Reviewed-on: https://gem5-review.googlesource.com/c/12905 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2018-10-18mem: Determine if an MSHR does a whole-line writeNikos Nikoleris
This patch adds support for determining whether the targets in an MSHR are 1) only writes and 2) whether these writes are effectively a whole-line write. This patch adds the necessary functions in the MSHR to allow for write coalescing in the cache. Change-Id: I2c9a9a83d2d9b506a491ba5b0b9ac1054bdb31b4 Reviewed-on: https://gem5-review.googlesource.com/c/12904 Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2018-10-18mem: Mark the guest endianness packet accessors as deprecated.Gabe Black
Change-Id: Iebefeb5b1ce905f2b45b30b7656d6a01d0724584 Reviewed-on: https://gem5-review.googlesource.com/c/13575 Maintainer: Gabe Black <gabeblack@google.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
2018-10-18null: Stop specifying an endianness in isa_traits.hh.Gabe Black
The NULL ISA doesn't really have an endianness. Now that the packet accessors which consumed that endianness are gone, we can get rid of that setting as well. Change-Id: I8dd4c7b8236b07df4458fea377865f30141121d4 Reviewed-on: https://gem5-review.googlesource.com/c/13466 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com>
2018-10-18mem: Explicitly specify the endianness in the abstract memory.Gabe Black
The accessors are used for debugging output. If we're using an ISA where there's an endianness, we use that explicitly, falling back to a binary dump if the size isn't supported. If not, then we just dump the data without interpretation regardless of size. Change-Id: Ib050c4c876ee41f17cfd14ad657150bf6ab1de39 Reviewed-on: https://gem5-review.googlesource.com/c/13464 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Gabe Black <gabeblack@google.com>
2018-10-17gpu-compute: Explicitly use little endian packet accessors.Gabe Black
The gpu ISA doesn't have a well defined endianness, but it really should. It seems that the GPU is only used with x86, and in that context it would be little endian. Change-Id: I1620906564a77f44553fbf6d788866e017b6054b Reviewed-on: https://gem5-review.googlesource.com/c/13463 Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com> Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>
2018-10-17arch: Include some additional headers in arch/generic/mmapped_ipr.cc.Gabe Black
These had been included transitively before. Change-Id: Ie420bc957e9abb5cd01fcf720fc1fda619d210f0 Reviewed-on: https://gem5-review.googlesource.com/c/13538 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-10-17dev: Remove using namespace TheISA in uart8250.cc.Gabe Black
Nothing in that file is in the TheISA namespace, so there's no reason to use using on it. Change-Id: I279c27af86509f75ac4e340956381041a0dbcdc4 Reviewed-on: https://gem5-review.googlesource.com/c/13537 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-10-17dev: Explicitly specify the endianness for packet accessors.Gabe Black
Generally speaking, the endianness of the data devices provide or accept is dependent on the device and not the ISA the system executes. This change makes the devices in dev pick an endianness rather than using the guest's. For the ISA bus and the UART, accesses are byte sized and so endianness doesn't matter. The ISA and PCI busses and the devices which use them are defined to be little endian. Change-Id: Ib0aa70f192e1d6f3b886d9f3ad41ae03bddb583f Reviewed-on: https://gem5-review.googlesource.com/c/13462 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-10-17python: Stop conditionally excluding code from pyobject.ccGabe Black
Now that the Ether* classes are included in all builds, there's no reason to conditionally compile code in pyobject.cc. Change-Id: If94602af71774b1f090a3344a633207f4b37d308 Reviewed-on: https://gem5-review.googlesource.com/c/13470 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-10-17dev: Build most of the networking devices in the NULL_ISA build.Gabe Black
The only part of these devices which are incompatible with other ISAs, with the possible exception of endianness transformation, is that the dist_iface implementation refers to ThreadContext methods and that class is heavily tied to the guest ISA. Only those few lines are excluded in a NULL_ISA build. Change-Id: Ic6d643fdbb792d0a996a37d75e027c5ce0ecd460 Reviewed-on: https://gem5-review.googlesource.com/c/13469 Reviewed-by: Gabor Dozsa <gabor.dozsa@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-10-17dev: Build the PCI device models even in NULL_ISA builds.Gabe Black
There are some minor ISA dependencies in the PCI device models, specifically that they use the set<> accessors on the packet objects. This actually compiles fine because the NULL ISA claims to be little endian, but really these accessors should be changed to use little endian all the time since that's what PCI is defined to use, not the guest endianness. The other types of accessors, specifically the ones that default to what the guest wants, should be excluded when building NULL_ISA, and, pending other dependencies, the NULL_ISA should no longer have an endianness associated with it. Change-Id: I0739122dbf67d109e7959553a1eff0239b090ca4 Reviewed-on: https://gem5-review.googlesource.com/c/13468 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-10-17arch: Get rid of the unused type AnyReg.Gabe Black
This type is defined for all the ISAs but isn't used by anything. Change-Id: I659a0c5abc7883d82fedd1cac2cd103612d315c8 Reviewed-on: https://gem5-review.googlesource.com/c/13539 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-10-17dev-arm: Don't panic when EOIR a non active PPIAdrien Pesle
GIC architecture specification says that writing EOIR with a not active irq it is an unpredictable behavior. So, just warn when it happens for a PPI case, like it is already done in SPI case. Change-Id: Icb1b8f5690d5e87b15c3b0fe2ca0d37fdd4085ee Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/13556 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-10-17dev-arm: Fix Gicv2 distributor group registerAdrien Pesle
For each bit in GICD_IGROUPR: value 0 means corresponding irq is group0 value 1 means corresponding irq is group 1. Change-Id: I15699d4bc89ff3df0e0bdb41154c0d0989dc2f63 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/13555 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-10-16systemc: Get rid of leftovers from unimplemented warnings past.Gabe Black
These warnings were removed when the functionality they warned about was implemented, but there were some leftovers like unnecessary includes and some helper functions which hid gem5 specific headers from the ext directory. Change-Id: Ic886ac0f1264687524e3a7b7eaab8836f318a5a2 Reviewed-on: https://gem5-review.googlesource.com/c/13398 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com>
2018-10-16systemc: Implement Object::simcontext().Gabe Black
Implement it as a nonstandard alias for the also non-standard sc_get_curr_simcontext. Change-Id: Ic9a51efa93f687e4b57d622247a5510136fab221 Reviewed-on: https://gem5-review.googlesource.com/c/13397 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com>
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