summaryrefslogtreecommitdiff
AgeCommit message (Collapse)Author
2018-11-29systemc: Make verify.py recognize a DEPS file in test dirs.Gabe Black
This file lists additional files beyond the sources that the test relies on, like files it uses when running. Change-Id: Ifc4958b26eed08689e0e72bd87f84388dbcf1898 Reviewed-on: https://gem5-review.googlesource.com/c/14516 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com>
2018-11-28base: Add missing overrides in statistics headerNikos Nikoleris
Change-Id: Id5ee2a970a3dceee1b7e24ce3b452b7fece87875 Signed-off-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/14619 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2018-11-28arch-arm: Add missing template declarationNikos Nikoleris
The lack of a template declaration for IllegalInstSetStateFault was causing errors when compiling with clang. Change-Id: If7f19d7e879330226c80df2baca73d88d818f673 Signed-off-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/14618 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
2018-11-28cpu: Added new stats to TAGE and LTAGE branch predictorsPau Cabre
They are basically used to tell wich component of the predictor is providing the prediction and whether it is correct or wrong Change-Id: I7b3db66535f159091f1b37d70c2d942d50b20fb2 Signed-off-by: Pau Cabre <pau.cabre@metempsy.com> Reviewed-on: https://gem5-review.googlesource.com/c/14535 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2018-11-28cpu: split LTAGE implementation into a base TAGE and a derived LTAGEPau Cabre
The new derived LTAGE is equivalent to the original LTAGE implementation The default values of the TAGE branch predictor match the settings of the 8C-TAGE configuration described in https://www.jilp.org/vol8/v8paper1.pdf Change-Id: I8323adbfd5c9a45db23cfff234218280e639f9ed Signed-off-by: Pau Cabre <pau.cabre@metempsy.com> Reviewed-on: https://gem5-review.googlesource.com/c/14435 Reviewed-by: Sudhanshu Jha <sudhanshu.jha@arm.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2018-11-28cpu,arch-arm: Initialise data membersRekai Gonzalez-Alberquilla
The value that is not initialized has a bogus value that manifests when using some debug-flags what makes the usage of tracediff a bit more challenging. In addition, while debugging with other techniques, it introduces the problem of understanding if the value of a field is 'intended' or just an effect of the lack of initialisation. Change-Id: Ied88caa77479c6f1d5166d80d1a1a057503cb106 Signed-off-by: Giacomo Gabrielli <giacomo.gabrielli@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/13125 Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
2018-11-28arch-arm: clang compilation fixesMatteo Andreozzi
Fix 1: std::pair constructor is not a constexpr in clang implementation Fix 2: static const templates need to be defined in their translation unit Change-Id: I3d9b9b47e1d148e44555f40e2e2aeff06707ff8f Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/14617 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
2018-11-28tests: Convert IniFile unit test to a GTestGiacomo Travaglini
Change-Id: I47d6c9cbae21877420a15ffcf8489e3c26959139 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/14615 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com>
2018-11-27hsail: Fix a warning/build failure for HSAIL_X86.Gabe Black
The Bitselect operation definition used ~ to invert the bits of a mask value, but if that mask value is of type bool, that generates a warning. This change casts that value to a uint64_t so that it can always have ~ applied to it. Change-Id: I7fbfc6ff264bc32a265f2724c772b8fae08590f7 Reviewed-on: https://gem5-review.googlesource.com/c/14655 Reviewed-by: Brandon Potter <Brandon.Potter@amd.com> Maintainer: Gabe Black <gabeblack@google.com>
2018-11-27arch, base, cpu, gpu, mem: Replace assert(0 or false with panic.Gabe Black
Neither assert(0) nor assert(false) give any hint as to why control getting to them is bad, and their more descriptive versions, assert(0 && "description") and assert(false && "description"), jury rig assert to add an error message when the utility function panic() already does that directly with better formatting options. This change replaces that flavor of call to assert with panic, except in the actual code which processes the formatting that panic uses (to avoid infinitely recurring error handling), and in some *.sm files since I don't know what rules those have to follow and don't want to accidentaly break them. Change-Id: I8addfbfaf77eaed94ec8191f2ae4efb477cefdd0 Reviewed-on: https://gem5-review.googlesource.com/c/14636 Reviewed-by: Brandon Potter <Brandon.Potter@amd.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2018-11-27sim-se: only implement getdentsFunc on supported hostsCiro Santilli
The implementation of the getdents syscall relies on SYS_getdents, which is not available on all archs, because the getdents syscall has been superseded by getdents64, and does not exist on newer archs such as aarch64. This leads the build to break on aarch64 hosts with error: error: 'SYS_getdents' was not declared in this scope Change-Id: I8701fb5b61c0418b14a9463ef135a391a7f7a9ba Reviewed-on: https://gem5-review.googlesource.com/c/14596 Reviewed-by: Brandon Potter <Brandon.Potter@amd.com> Maintainer: Brandon Potter <Brandon.Potter@amd.com>
2018-11-27systemc: set endianess to fix build for ARM hostCiro Santilli
ARM architectures were not covered in the endianess #if cases, which lead the build to fail on an arm host with message: error The file boost/detail/endian.hpp needs to be set up for your CPU type. Change-Id: Id012cf37810da113174a51746e290e25138739cb Reviewed-on: https://gem5-review.googlesource.com/c/14595 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com>
2018-11-27base: Add some functions to convert floats to bits and vice versa.Gabe Black
These make it easier to extract the binary representation of floats and doubles, and given a binary representation convert it back again. The versions with a size prefix are safer to use since they make it clear what size inputs/outputs are expected. The versions without are to make writing generic code easier in case the same code snippet, templated function, etc., needs to be applied in both circumstances. Change-Id: Ib1f35a7e88e00806a7c639c211c5699b4af5a472 Reviewed-on: https://gem5-review.googlesource.com/c/14455 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Gabe Black <gabeblack@google.com>
2018-11-26mem-cache: Add setters to validate and secure blockDaniel R. Carvalho
In order to allow polymorphism of the block these two functions have been added, and all direct status assignments to these bits have been substituted. We also assert that the block has been invalidated before insertion. Then the block is validated in the insertion. Change-Id: Ie7be42408721ad4c2c9dc880f82a62cb594f8668 Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br> Reviewed-on: https://gem5-review.googlesource.com/c/14362 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2018-11-22cpu: Made LTAGE parameters configurablePau Cabre
This includes TAGE tag sizes, TAGE table sizes, U counters reset period, loop predictor associativity, path history size, the USE_ALT_ON_NA size and the WITHLOOP size Change-Id: I935823f0a5794f5d55b744263798897a813dc1bd Signed-off-by: Pau Cabre <pau.cabre@metempsy.com> Reviewed-on: https://gem5-review.googlesource.com/c/14417 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2018-11-22cpu: Fixed useful counter handling in LTAGEPau Cabre
Increased to 2 bits of useful counter per TAGE entry as described in the LTAGE paper (and made the size configurable) Changed how the useful counters are incremented/decremented as described in the LTAGE paper Change-Id: I8c692cc7c180d29897cb77781681ff498a1d16c8 Signed-off-by: Pau Cabre <pau.cabre@metempsy.com> Reviewed-on: https://gem5-review.googlesource.com/c/14215 Reviewed-by: Ilias Vougioukas <ilias.vougioukas@arm.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2018-11-22cpu: Fixes on the loop predictor part of LTAGEPau Cabre
Fixed the following fields of the loop predictor entries as described on the LTAGE paper: - Age counter (it was 3 bits and it should be 8 bits) - Tag (it was 16 bits and it should be 14 bits). Also some times it used int variables and some times uint16_t, leading to wrong behaviour - Confidence counter (it was 2 bits ins some parts of the code and 3 bits in some other parts. It should be 2 bits) - Iteration counters (they were 16 bits and they should be 14 bits) All the new sizes are now configurable Change-Id: I8884c7454c1e510b65160eb4d5749d3259d34096 Signed-off-by: Pau Cabre <pau.cabre@metempsy.com> Reviewed-on: https://gem5-review.googlesource.com/c/14216 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2018-11-21x86: Get rid of a problematic DPRINTF in PremFp.Gabe Black
This DPRINTF shouldn't be necessary since it shows the operands and results of the instruction which the trace should already make available. Also by passing the destination register to DPRINTF, the ISA parser will assume that it's also a source when tracking dependencies. Change-Id: I820387c82578bdbb8d2e3d91652a6c0185077f54 Reviewed-on: https://gem5-review.googlesource.com/c/14475 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Gabe Black <gabeblack@google.com>
2018-11-20sim: Deschedule existing events when destructing an event queue.Gabe Black
Other objects in the simulation may try to deschedule their events when destructed, and if they're cleaned up after the event queue is then they might try to deschedule events on an event queue that no longer exists. Change-Id: I9452ce52fba78297ce3dc4b3884289b5e2f2574d Reviewed-on: https://gem5-review.googlesource.com/c/14400 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Gabe Black <gabeblack@google.com>
2018-11-19base: Don't let exceptions leak from the to_number utility function.Gabe Black
This function catches a couple types of exceptions the functions it calls might throw, but if one that it doesn't catch is thrown, then it will propogate that exception to its own callers, and not initialize the value it was asked to convert. This might be considered desirable behavior since it lets errors propogate and avoids handling them in code that might not know the context of when it's called. On the other hand, it upsets g++ since it thinks that there might be an uninitialized value used elsewhere, even though that value will only be uninitialized if an exception is propogating, and the code that would use it is after a point where that exception would have been caught and execution would have resumed. To satisfy g++ and to also avoid silently hiding errors, this change adds a catch all which will panic if an unexpected exception is raised. Change-Id: Ie94dcef3a50f7902566328a3fa2eac59b3cf9aad Reviewed-on: https://gem5-review.googlesource.com/c/14399 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2018-11-19systemc: Stop explicitly adding the systemc ext dir to CPPPATH.Gabe Black
That's now handled automatically when the native systemc API is enabled. Change-Id: If1f88929af335a40554a9fd8df6f68aa1a4c0ba4 Reviewed-on: https://gem5-review.googlesource.com/c/14398 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Gabe Black <gabeblack@google.com>
2018-11-19systemc: Put systemc headers in the include path when supported.Gabe Black
When the native systemc API support is built in, put the systemc and systemc.h header files in the include path so they can be used as normal. We don't want any external systemc headers being included and getting mixed in with our local ones. Change-Id: I5fc01ff5f069cfadb7c19a9dead13e7ce7272976 Reviewed-on: https://gem5-review.googlesource.com/c/14397 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Gabe Black <gabeblack@google.com>
2018-11-19systemc: Increase the stack size for the sc_main fiber to 8MB.Gabe Black
This is a reasonable size for a stack, and the default size for a stack on Linux as determined by some quick Googling. The sc_main fiber would normally use the primary program stack if run under the standard systemc implementation, and so might expect to have more room to play with. Change-Id: Ie12344939e7b249da203630ebc7dc773a387d716 Reviewed-on: https://gem5-review.googlesource.com/c/14396 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Gabe Black <gabeblack@google.com>
2018-11-18base: Set up a guard page for fiber stacks.Gabe Black
This will help detect stack overflow for fibers. Change-Id: Iff2b102120ec351709e495291d6bead597f8d10c Reviewed-on: https://gem5-review.googlesource.com/c/14395 Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br> Maintainer: Gabe Black <gabeblack@google.com>
2018-11-18mem-cache: a missing cast was truncating addressesJavier Bueno
High bits were truncated when computing the block address Change-Id: Iab2a4c6063ece2d1d4c24ce5686045a6d6d35434 Reviewed-on: https://gem5-review.googlesource.com/c/14415 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2018-11-17cpu: Fix LTAGE max number of allocations on updatePau Cabre
The LTAGE paper states that only one TAGE entry can be allocated when updating Change-Id: I6cfb4d80ce835e93d4bf5099ef88a7d425abaddd Signed-off-by: Pau Cabre <pau.cabre@metempsy.com> Reviewed-on: https://gem5-review.googlesource.com/c/14195 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Ilias Vougioukas <ilias.vougioukas@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-11-17configs: Added an option for choosing branch predictor typePau Cabre
Added the parameter "--bp-type" to set the branch predictor type Added the parameter "--list-bp-types" to list all the available branch predictor types Change-Id: Ia6aae90c784aef359b6d8233c8383cd7a871aca1 Signed-off-by: Pau Cabre <pau.cabre@metempsy.com> Reviewed-on: https://gem5-review.googlesource.com/c/14015 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-11-16sim: Fix data type of ticks per second before passing it to C++Srikant Bharadwaj
Casts ticks per second value to int before passing it to C++. Python throws an error because of incompatible type because of the recent change. Change-Id: Ibcaf8c327f1be0dba38763975d389584addd8373 Reviewed-on: https://gem5-review.googlesource.com/c/14375 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com>
2018-11-16mem: avoid calling regStat twice on a QoSPolicyMatteo Andreozzi
Change-Id: I216c57073fabe29c3f898a5d89cee41efd4277d5 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/13696 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2018-11-16cpu: Fix the usage of const DynInstPtrRekai Gonzalez-Alberquilla
Summary: Usage of const DynInstPtr& when possible and introduction of move operators to RefCountingPtr. In many places, scoped references to dynamic instructions do a copy of the DynInstPtr when a reference would do. This is detrimental to performance. On top of that, in case there is a need for reference tracking for debugging, the redundant copies make the process much more painful than it already is. Also, from the theoretical point of view, a function/method that defines a convenience name to access an instruction should not be considered an owner of the data, i.e., doing a copy and not a reference is not justified. On a related topic, C++11 introduces move semantics, and those are useful when, for example, there is a class modelling a HW structure that contains a list, and has a getHeadOfList function, to prevent doing a copy to an internal variable -> update pointer, remove from the list -> update pointer, return value making a copy to the assined variable -> update pointer, destroy the returned value -> update pointer. Change-Id: I3bb46c20ef23b6873b469fd22befb251ac44d2f6 Signed-off-by: Giacomo Gabrielli <giacomo.gabrielli@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/13105 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2018-11-15mem-cache: fix invalid iterator accessJavier Bueno
An iterator was assigned end() and then it was used to access its corresponding element. Change-Id: I87246cf56cbc694dd6b4e2cabbe84a08429d2ac3 Reviewed-on: https://gem5-review.googlesource.com/c/14361 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2018-11-15mem-cache: Make StridePrefetcher use Replacement PoliciesDaniel
Previously StridePrefetcher was only able to use random replacement policy. This change allows all replacement policies to be applied to the pc table. Change-Id: I8714e71a6a4c9c31fbca49a07a456dcacd3e402c Signed-off-by: Daniel <odanrc@yahoo.com.br> Reviewed-on: https://gem5-review.googlesource.com/c/14360 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2018-11-15mem-cache: Add invalidation function to StrideEntryDaniel
Add invalidation function to StrideEntry so that every entry can be invalidated appropriately. Change-Id: I38c42b7d7c93d839f797d116f1d2c88572123c0e Signed-off-by: Daniel <odanrc@yahoo.com.br> Reviewed-on: https://gem5-review.googlesource.com/c/14359 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2018-11-15mem-cache: Make PCTable context independentDaniel
Move the unordered_map outside of the PCTable, as it belongs to the StridePrefetcher. By doing so we are moving towards a table that ressembles the ones of the Tags classes. Some functions have been moved from the prefetcher to the PCTable, as they didn't belong there. As such, they have been renamed to remove the unnecessary prefix. Change-Id: I3e54bc7dee65e1f78d96b0d548ac8345b7bd4364 Signed-off-by: Daniel <odanrc@yahoo.com.br> Reviewed-on: https://gem5-review.googlesource.com/c/14358 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2018-11-15mem-cache: Vectorize StridePrefetcher's entries.Daniel
Turn StridePrefetcher::PCTable::entries into a vector of vectors. Change-Id: I2a4589a76eb205910c43723638b7989eddd5ca24 Reviewed-on: https://gem5-review.googlesource.com/c/14357 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2018-11-15mem-cache: Return entry in StridePrefetcher::pcTableHit()Daniel
Return a pointer to the entry instead of returning a boolean and passing a pointer reference. As a side effect, change the name of the function to be more descriptive of the functionality. Change-Id: Iad44979e98031754c1d0857b1790c0eaf77e9765 Signed-off-by: Daniel <odanrc@yahoo.com.br> Reviewed-on: https://gem5-review.googlesource.com/c/14356 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2018-11-15mem-cache: Cleanup prefetchersDaniel
Prefetcher code had extra variables, dependencies that could be removed, code duplication, and missing overrides. Change-Id: I6e9fbf67a0bdab7eb591893039e088261f52d31a Signed-off-by: Daniel <odanrc@yahoo.com.br> Reviewed-on: https://gem5-review.googlesource.com/c/14355 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2018-11-15scons: add --gold-linker to link with the gold linkerCiro Santilli
This option can significantly speedup link time on Linux systems, which is the main bottleneck to rebuild after small changes. Change-Id: I3b0bdd61f7dcef0d73629c8ee2ee98091953fec3 Reviewed-on: https://gem5-review.googlesource.com/c/14075 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Gabe Black <gabeblack@google.com>
2018-11-14cpu: Fixed ratio of pred to hyst bits for LTAGE BimodalPau Cabre
The LTAGE paper states 1 hyst bit shared for 4 pred bits. Made this ratio configurable use 4 by default. Also changed the Bimodal structure to use two std::vector<bool> (one for pred and one for hyst bits) Change-Id: I6793e8e358be01b75b8fd181ddad50f259862d79 Signed-off-by: Pau Cabre <pau.cabre@metempsy.com> Reviewed-on: https://gem5-review.googlesource.com/c/14120 Reviewed-by: Ilias Vougioukas <ilias.vougioukas@arm.com> Reviewed-by: Sudhanshu Jha <sudhanshu.jha@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-11-14mem-cache: Remove Cache dependency from TagsDaniel R. Carvalho
Tags do not need to be aware of caches. Change-Id: Ib6a082b74dcd9b2f10852651634b59512732fb2a Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br> Reviewed-on: https://gem5-review.googlesource.com/c/14296 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2018-11-14mem-cache: Move access latency calculation to CacheDaniel R. Carvalho
Access latency was not being calculated properly, as it was always assuming that for hits reads take as long as writes, and that parallel accesses would produce the same latency for read and write misses. By moving the calculation to the Cache we can use the write/ read information, reduce latency variables duplication and remove Cache dependency from Tags. The tag lookup latency is still calculated by the Tags. Change-Id: I71bc68fb5c3515b372c3bf002d61b6f048a45540 Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br> Reviewed-on: https://gem5-review.googlesource.com/c/13697 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2018-11-14arch-arm: Print register name when warning on AT instructionsGiacomo Travaglini
With this patch we don't print anymore the enum value when warning on any AT instruction usage, but we print the sys reg name instead Change-Id: Ic6831b98ad6b0582be69883dc9519a9d3324da30 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Anouk Van Laer <anouk.vanlaer@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/14316 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-11-14mem-cache: implement a probe-based interfaceJavier Bueno
The HW Prefetcher of a cache can now listen events from their associated CPUs and from its own cache. Change-Id: I28aecd8faf8ed44be94464d84485bd1cea2efae3 Reviewed-on: https://gem5-review.googlesource.com/c/14155 Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2018-11-14sim: Move BitUnion overloading to show/parseParamsGiacomo Travaglini
This patch is moving template overloading for BitUnions into the showParam, parseParams functions. Henceforth BitUnion types will use the common param wrapper. This patch implicitly implements (UN)SERIALIZE_CONTAINER for BitUnions. Change-Id: I0e1faadb4afd4dc9de5dc5fca40041e349c9ba73 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/13636 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-11-14sim: Move paramIn/Out definition to header fileGiacomo Travaglini
This patch is moving the definitions of paramIn/Out templates to the header file. In this way we gain: 1) We don't have to do explicit instantiation anymore for user defined types. This spares us from including data type header files into serialize.cc 2) We can overload show/parseParam for BitUnions or any other type that requires special handling when serializing. Just by overloading the two templates we get all the containers' (list, vector, array..) serialization for free 2) gtest: With the idea of adding unit tests for Serializable objects, we can avoid importing serialize.cc and just redefine Serializable methods in the test source, implementing a Serializable stub Change-Id: I45a9bb87d5ef886a3668fd477005cd105f612e36 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/13635 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-11-13cpu: Fixed PC shifting on LTAGE branch predictorPau Cabre
The PC needs to be shifted according to the instShiftAmt parameter Change-Id: I272619c093695b56cf7f8ff7163e3b5d23205d16 Signed-off-by: Pau Cabre <pau.cabre@metempsy.com> Reviewed-on: https://gem5-review.googlesource.com/c/14035 Reviewed-by: Sudhanshu Jha <sudhanshu.jha@arm.com> Reviewed-by: Ilias Vougioukas <ilias.vougioukas@arm.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-11-13mem-cache: Align how we handle requests in atomic with timingNikos Nikoleris
Requests, for which a cache has already committed to respond do not perform any lookups. Previously in atomic mode the packet would pay the lookup latency while in timing it wouldn't. This patch aligns recvAtomic with recvTimingReq and removes the lookup latency from the the handling of such requests. Change-Id: I50a0631f8058e5086d94d55af0e1788a60e2883f Signed-off-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/14175 Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br> Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
2018-11-12systemc: Push python headers on top of sourcesGiacomo Travaglini
Some build failures has been seen after USE_SYSTEMC being True by default and that has been caused by double definition of _XOPEN_SOURCE and _POSIX_C_SOURCE in some python versions (like 2.7.5, 2.7.13) and /usr/include/features.h (used by gcc) Python definition should preceed features.h one, since the latter will manually #undef them before #define them. Change-Id: I774711aaf8145df9ad7677a393a60cf3662d6816 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/14095 Maintainer: Gabe Black <gabeblack@google.com>
2018-11-12systemc: Stop using python to set/manage the global time resolution.Gabe Black
Now that that's managed in c++, we can do that directly without having to depend on the python code being available, the code which lets us call from c++ to python, or for the embedded python interpretter to have started running and have loaded the appropriate modules. Change-Id: Ied110d8f22181095f8c0c645636a9bd67964263e Reviewed-on: https://gem5-review.googlesource.com/c/14056 Maintainer: Gabe Black <gabeblack@google.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
2018-11-12sim: Push the global frequency management code into C++.Gabe Black
That makes it available when python is left out, and makes it available to c++ code without having to call back into python. Change-Id: If82e7e8eff526f2b957f84afe046e1d56fed4aa2 Reviewed-on: https://gem5-review.googlesource.com/c/14055 Reviewed-by: Srikant Bharadwaj <srikant.bharadwaj@amd.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-22 14:48:54 +0000