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AgeCommit message (Expand)Author
2018-06-14ruby: Revamp standalone SLICC scriptJason Lowe-Power
2018-06-14arch-arm: Adapting IllegalExecution fault for AArch32Giacomo Travaglini
2018-06-14arch-arm: Add Illegal Execution flag to PCStateGiacomo Travaglini
2018-06-14arch-arm: Read APSR in User ModeGiacomo Travaglini
2018-06-14system-arm: Split the VExpress_GEM5_V1 base dtsAndreas Sandberg
2018-06-14dev-arm: Add new VExpress_GEM5_V1_Base PlatformRohit Kurup
2018-06-14cpu-minor: Remove redundant thread startup callAndreas Sandberg
2018-06-14dev-arm: Remove deprecated GIC test interfacesAndreas Sandberg
2018-06-13tests: Make "UnitTest"s more like GTest so they can be in other dirs.Gabe Black
2018-06-13mem-cache: Remove unnecessary cast in SectorTags::findVictimNikos Nikoleris
2018-06-13arch-arm: Fix missing Request allocationGiacomo Travaglini
2018-06-13mem-cache: Insert on block allocationDaniel R. Carvalho
2018-06-13mem-cache: Make packet const in insertBlockDaniel R. Carvalho
2018-06-13mem-cache: Create Sector CacheDaniel R. Carvalho
2018-06-12tests: add some pthread and std::thread unit testsTuan Ta
2018-06-12ruby: Fix initial weight in weighted LRUDaniel R. Carvalho
2018-06-11misc: Using smart pointers for memory RequestsGiacomo Travaglini
2018-06-11misc: Substitute pointer to Request with aliased RequestPtrGiacomo Travaglini
2018-06-08mem-cache: Change Cache block tag checkDaniel R. Carvalho
2018-06-08mem-cache: Use secure bit in findVictimDaniel R. Carvalho
2018-06-08mem-cache: Move tagsInUse to childrenDaniel R. Carvalho
2018-06-08mem-cache: Return evictions along with victimsDaniel R. Carvalho
2018-06-08mem-cache: Use ReplaceableEntry in findBlockBySetAndWayDaniel R. Carvalho
2018-06-08sim: Rename the SimObject cxx_bases field to cxx_extra_bases.Gabe Black
2018-06-07dev-arm: Add a VirtIO MMIO device to VExpress_GEM5_V1Andreas Sandberg
2018-06-07dev-arm: Add a MMIO transport interface for VirtIOAndreas Sandberg
2018-06-07dev-arm: Add a GIC interrupt adaptorAndreas Sandberg
2018-06-06arch-arm: Remove dead doingStage2 variable in PT walkerAndreas Sandberg
2018-06-06system-arm: Update gem5 timer interrupt specificationAndreas Sandberg
2018-06-06arch-arm: Perform stage 2 lookups using the EL2 stateAndreas Sandberg
2018-06-06arch-arm: Respect EL from translation typeAndreas Sandberg
2018-06-06arch-arm: Fix page size handling when merging stage 1 and 2Andreas Sandberg
2018-06-06dev, arm: Add support for HYP & secure timersAndreas Sandberg
2018-06-06arch-arm: Adjust breakpoint EC depending on source stateAndreas Sandberg
2018-06-01mem-cache: Privatize extractSetDaniel R. Carvalho
2018-06-01mem-cache: Create an address aware TempCacheBlkDaniel R. Carvalho
2018-06-01mem-cache: Fix secure bit modificationDaniel R. Carvalho
2018-05-31mem-cache: Replace block visitor with std::functionNikos Nikoleris
2018-05-31mem-cache: Fix include directives in the cache related classesNikos Nikoleris
2018-05-31mem-cache: Add a non-coherent cacheNikos Nikoleris
2018-05-31mem-cache: Move cache bypass mechanism to the portsNikos Nikoleris
2018-05-31mem-cache: Adopt a more sensible cache class hierarchyNikos Nikoleris
2018-05-31mem-cache: Add helper function to perform evictionsNikos Nikoleris
2018-05-31mem-cache: Delegate block invalidation to block allocationNikos Nikoleris
2018-05-31mem-cache: Refactor the recvAtomic functionNikos Nikoleris
2018-05-31mem-cache: Refactor the cache recvTimingReq functionNikos Nikoleris
2018-05-31mem-cache: Refactor the cache recvTimingResp functionNikos Nikoleris
2018-05-31mem-cache: Fix RandomReplDataDaniel R. Carvalho
2018-05-30gpu-compute: use X86ISA::TlbEntry over GpuTlbEntryBrandon Potter
2018-05-30dev: Exit correctly in dist-gem5 for SE modeMichael LeBeane
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