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2018-11-07misc: Update workflow requirements in CONTRIBUTING.mdTony Gutierrez
Change-Id: I5394ef58930fccea343414964c1fc3e18829d609 Reviewed-on: https://gem5-review.googlesource.com/c/13755 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2018-11-07arch-arm: Deprecate usage of legacy bootloader patchingGiacomo Travaglini
This patch is implicitly deprecating the usage of bootloader patching, which is injecting instructions from gem5 into the bootloader binary. This was probably meant to provide a dynamic bootloader entry point. This is not needed in ARMv8.0, since we can simply update the ArmSystem::resetAddress with the bootloader entry point. Change-Id: I0c469873b8d69f7b49a7383e0754468bc1f2bd72 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/14001 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-11-07arch-arm: ArmSystem::resetAddr64 renamed to be used in AArch32Giacomo Travaglini
ARMv8 differs from ARMv7 with the presence of RVBAR register, which contains the implementation defined reset address when EL3 is not implemented. The entry 0x0 in the AArch32 vector table, once used for the Reset Vector, is now marked as "Not used", stating that it is now IMPLEMENTATION DEFINED. An implementation might still use this vector table entry to hold the Reset vector, but having a Reset address != than the general vector table (for any other exception) is allowed. At the moment any Reset exception is still using 0 as a vector table base address. This patch is extending the ArmSystem::resetAddr64 to ArmSystem::resetAddr so that it can be used for initializing MVBAR/RVBAR. In order to do so, we are providing a specialized behavior for the Reset exception when evaluating the vector base address. Change-Id: I051a730dc089e194db3b107bbed19251c661f87e Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/14000 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-11-07arch-arm: Implement AArch32 RVBARGiacomo Travaglini
RVBAR has been added to the system register list since ARMv8.0-A. It is implemented only if the highest Exception Level is different (minor) than EL3. If that's not the case, MVBAR is used. Since the two registers are mutually exclusive (depending on the presence of EL3), they share the same coprocessor numbers: p15, 0, c12, c0, 1 Rather than introducing a new register alias, we overload MVBAR so that it is treated as RVBAR if ArmSystem::highestEL() < EL3. This patch is changing the MiscReg info so that EL1 or EL2 access MVBAR (as RVBAR). N.B MVBAR is RW, whereas RVBAR is RO Change-Id: Ida3070413fd151ce79c446e99a2a389298d5f5bd Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/13999 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-11-07arch-arm: Remove SCTLR.VE bitGiacomo Travaglini
ARMv8 has removed SCTLR.VE bit which is now hardcoded to 0. We are removing it from gem5 since we were not handling it anyway. Change-Id: Ibde2db45c7f8add4a3188f2cb8c23701a6088d03 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/13998 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-11-07arch-arm: Refactor ISA::clear by adding a ISA::clear32 methodGiacomo Travaglini
The patch is also moving some initialization code to be used by AArch64 as well since the registers are mapped to AArch64 ones. Change-Id: I0089df25275434172c6e0e9cb125ee535c04d1b8 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/13997 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-11-07arch-arm: Remove MISCREG commented numbersGiacomo Travaglini
Having an enum number might be useful in case we wanted to know how many miscregs we have, but on the other hand it makes it tedious to update the register list, since every commented number must be bumped. This patch is removing the comments holding the MISCREG numbers Change-Id: Ic5aba93885e4b8d6cb3bd6a4c49900b9e5474276 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/13996 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-11-07systemc: Fix some paths in the tlm SCons(script|struct).Gabe Black
The code in util/systemc was moved into a subdirectory recently. The scons support here referred to it, and needed to be updated. Change-Id: Ib457d9bdafb2bba5058e6ecf99b9d33b3072c5b3 Reviewed-on: https://gem5-review.googlesource.com/c/13955 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2018-11-06mips: Change the integer and fp register widths to be 64 bits.Gabe Black
This makes them more consistent with the other architectures, helping to facilitate having a single, unified type across ISAs in the future. Change-Id: I65efb10e39d453281b8429eeedbb46fa6b023a2b Reviewed-on: https://gem5-review.googlesource.com/c/13620 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2018-11-06mips: Clean up type overrides for operands.Gabe Black
For operands which default to uw (uint32_t), there's no reason to explicitly specify that all over the place. Also, when assigning to a 32 bit value which is supposed to be the full width of the resulting register, there's no reason to override the value to be signed. If the value is expanded into a larger value, then extra bits may get set unintentionally through sign extension. Even if an instruction produces a value which should be interpreted as signed, it will still only produce a value of a certain predefined width, even if that answer ends up stored in a larger variable. Change-Id: I048d68c5dd08a1d40e8117ae9d36d70e05ec21c8 Reviewed-on: https://gem5-review.googlesource.com/c/13618 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Gabe Black <gabeblack@google.com>
2018-11-06mips: Explicitly truncate the syscall return value down to 32 bits.Gabe Black
The IntReg type is 32 bits, and using it to cast the syscall return value is appropriate, but we're attempting to get rid of the ISA specific register types. Change-Id: I42496dd2cc086a6b718e1ce087fef81bb897d02f Reviewed-on: https://gem5-review.googlesource.com/c/13619 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2018-11-05null: Claim to use 64 bit floating point registers.Gabe Black
The NULL ISA doesn't actually have registers, so this setting doesn't matter. By making it 64 bits the ISA is more compatible with the other ISAs. Change-Id: I2c9b6d9a6f612719b8b00eb9dbed55fa2159e9b5 Reviewed-on: https://gem5-review.googlesource.com/c/13617 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2018-11-05sparc: Switch the FloatReg and FloatRegBits types to be 64 bit.Gabe Black
These types aren't used by the ISA itself since they're defined to be particular primitive types in the ISA description. This just affects code outside of the ISA which work with those types of registers. Change-Id: I4f62ab8fe04184cc23845090c82b250145a71747 Reviewed-on: https://gem5-review.googlesource.com/c/13616 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2018-11-05base: Add standard types for floating and nonfloating point register values.Gabe Black
These should be used instead of the ISA specific ones, and should be at least as large as the largest primitive register type in all the ISAs. Change-Id: Iaac104eef74eabcdd87787b1cdf8bea22d449eda Reviewed-on: https://gem5-review.googlesource.com/c/13615 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Gabe Black <gabeblack@google.com>
2018-11-05systemc: Enable systemc support by default.Gabe Black
Change-Id: I9375518a54e14413a499d065f5bc5e1031834c81 Reviewed-on: https://gem5-review.googlesource.com/c/13535 Maintainer: Gabe Black <gabeblack@google.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
2018-11-05systemc: Explicitly keep the sc_port bind alongside sc_in's version.Gabe Black
The sc_in bind function was hiding the one from sc_port by changing the const-ness of its parameter. This change explicitly exposes the underlying sc_port version, and keeps it alongside the new sc_in version. This seems mildly dangerous and undesirable because now there are two very similar functions which would both need to be overridden in order to get new behavior, but I don't think it's any more dangerous and undesirable than as (perhaps unintentionally) specified in the standard. Change-Id: Ib42a1f8e70bc97abeeeb8d614e71c4019b3a2323 Reviewed-on: https://gem5-review.googlesource.com/c/13880 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com>
2018-11-05systemc: Change how SC_BIND_PROXY_NIL is initialized.Gabe Black
The previous implementation dereferenced a null pointer to create a reference which would then have its address taken in the sc_bind_proxy constructor. clang says that that uses undefined behavior, so this change adds a default constructor which initializes the two contained pointers to null explicitly. We have to hope systemc code doesn't play around with sc_bind_proxy too much and doesn't accidentally use this constructor unintentionally, but it seems like the least bad possible solution which makes clang happy. Change-Id: Ic59603495fe7a406586a18ce44de979f84089bcd Reviewed-on: https://gem5-review.googlesource.com/c/13879 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com>
2018-11-05systemc: Get rid of implementations for some disabled sc_vector methods.Gabe Black
These don't need to exist, and the specifics of their stub implementations were upsetting clang. Change-Id: Ib38a39c5cfbc2e1647cfb6ed14c660e10df2b1c3 Reviewed-on: https://gem5-review.googlesource.com/c/13878 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com>
2018-11-05systemc: Move a function after the class it uses internally.Gabe Black
The class was defined, but only later in the file. By putting the function definition later, clang stops reporting an error. Change-Id: Id4dd1ec3f3a06f4d1dc10ef4ff8c545d98a6ae12 Reviewed-on: https://gem5-review.googlesource.com/c/13877 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com>
2018-11-05systemc: Get rid of an unused private member in sc_clock.Gabe Black
It's not useful, and having it makes clang upset. Change-Id: I51366fd18a287e186c88f08af5c6ba8692779003 Reviewed-on: https://gem5-review.googlesource.com/c/13876 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com>
2018-11-05mem-cache: Rename the tag class init function to tagsInit.Gabe Black
Since the tag classes are subclasses of SimObject, they inherit an init function which does generic initialization at simulation startup and which doesn't take any parameters. A new function was added which does take a parameter, and which is just for doing tag specific initialization as triggered by the base cache. These two names clashed, and clang complained that the tag local name was hiding the SimObject name (which it was). Change-Id: I399775aceaf8f1a8e2646d434facef22e6d3e7d0 Reviewed-on: https://gem5-review.googlesource.com/c/13875 Reviewed-by: Gabe Black <gabeblack@google.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Gabe Black <gabeblack@google.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2018-11-05mem: Use Packet writing functions instead of memcpyDaniel R. Carvalho
Classes were using memcpy instead of the Packet functions created for writing to/from the packet. This allows these writes to be better checked and tracked. This also fixes a bug in MemCheckerMonitor, which was using the incorrect type for the packet pointer. Change-Id: I5bbc8a24e59464e8219bb6d54af8209e6d4ee1af Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br> Reviewed-on: https://gem5-review.googlesource.com/c/13695 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2018-11-05mem-cache: Fix double block invalidationDaniel R. Carvalho
Block was being invalidated twice when not a tempBlock. Make explicit that the else case is only to be applied when handling the tempBlock, as otherwise the Tags should be taking care of the invalidation. Change-Id: Ie7603fdbe156c54e94bbdc83541b55e66f8d250f Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br> Reviewed-on: https://gem5-review.googlesource.com/c/13895 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2018-11-05arch, arm: Return s1Req upon fault in s2LookupAnouk Van Laer
When a s2Lookup object is created, a new request is created, based upon the original, stage 1 request sent out by the CPU. When a fault occurs during the second stage of translation, this new request is returned. This can lead to issues with the O3 CPU. The O3 fetch stage will not acknowledge the fault as it is a different request than the one it sent out and does not contain a contextID. This commit rectifies this. Change-Id: I21cb7377a59aed9d90d99f048b2106eaf219e93a Reviewed-by: Ciro Santilli <ciro.santilli@arm.com> Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/13782 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-11-05arch, arm: Effect of AT instructions on descriptor handlingAnouk Van Laer
Some address translation instructions will stop translation after the 1st stage and intercept the IPA, even in the presence of stage 2 (eg AT S1E1). However, in the case of a TLB miss, the table descriptors still need to be translated from IPA to PA to avoid fetching the wrong addresses. This commit splits whether IPA->PA translation is required for the VA and/or for the table descriptors. Change-Id: Ie53cdc00585f116150256f1d833460931b3bfb7d Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/13781 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-11-02util: Add some examples for using systemc code within gem5.Gabe Black
These examples have comments inside them that explain what they do. There's also a README file which explains how to use the examples generally, and at a high level what each one does. Change-Id: I223963dc1c190289986b2ee5705910dbcad4a4c9 Reviewed-on: https://gem5-review.googlesource.com/c/13376 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com>
2018-11-02util: Move the existing systemc example into a subdirectory.Gabe Black
This example is for how to embed gem5 within systemc and make it use the systemc event queue. This used to be the only method of using gem5 and systemc together, but now that there are other options, it's ambiguous to have it as the only thing in the util/systemc directory. This change moves it into a gem5_within_systemc subdirectory which clearly shows what type of integration that example corresponds with. Change-Id: I426d68ccb618397d820bef492cbb1ff8ef4a979b Reviewed-on: https://gem5-review.googlesource.com/c/13375 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com>
2018-10-30syscall_emul: fix openat when directory does not end in "/"Ciro Santilli
Before this commit, the following code: dir_fd = open(".", O_DIRECTORY); file_fd = openat(dir_fd, "ble", O_CREAT, S_IRUSR | S_IWUSR); would create a file called ".ble" in the current working directory, instead of the correct "ble". Change-Id: I1525a088d49744e29b760387afabef9f1ac98646 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/13005 Reviewed-by: Brandon Potter <Brandon.Potter@amd.com> Maintainer: Brandon Potter <Brandon.Potter@amd.com>
2018-10-29syscall_emul: implement arm openatCiro Santilli
This is especially important because the Ubuntu 18.04 packaged arm-linux-gnueabihf-gcc uses the system call on the program initialization, which leads all programs to fail with: fatal: syscall openat (#322) unimplemented. Change-Id: I5596162ad19644df7b6d21f2a46acc07030001ae Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/13004 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-10-29arch-arm: FIXUP for the add PRFM PST instruction commitYuetsu Kodama
Change-Id: I898e5b565c6591f88ae732b24713aeae2c827cbd Reviewed-on: https://gem5-review.googlesource.com/c/13815 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-10-26mem-ruby: Fix MOESI_CMP_directory in ports orderNikos Nikoleris
To avoid deadlocks ruby objects typically prioritize the handling of responses to all other events. The order in which in_port statements are written determine the order in which they are handled. This patch fixes the order of in_order statements for the L2 cache in the MOESI_CMP_directory. Change-Id: I62248b0480a88ac2cd945425155f0961a1cf6cb1 Signed-off-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/13595 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2018-10-26arch-arm: We add PRFM PST instruction for armyuetsu.kodama
Note current PRFM supports only PLD, but PST (prefetch for store) is also important for latency hiding. We also bug fix in disassembler to display prfop correctly. Change-Id: I9144e7233900aa2d555e1c1a6a2c2e41d837aa13 Signed-off-by: Yuetsu Kodama <yuetsu.kodama@riken.jp> Reviewed-on: https://gem5-review.googlesource.com/c/13675 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-10-26arch-arm: IMPDEF for SYS instruction with CRn = {11, 15}Giacomo Travaglini
According to the arm arm, a SYS instruction (op0 = 1) with CRn = (11 or 15) is implementation defined; this makes it trappable by having HCR_EL2.TIDCP = 1. Change-Id: Idd94ac345fee652ee6f8c0a7eb7b06ac75ec38ef Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/13780 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-10-26arch-arm: AArch64 Instruction for MISCREG_IMPDEF_UNIMPLGiacomo Travaglini
While there is a AArch32 class for instructions accessing implementation defined registers, we are lacking for the AArch64 counterpart. we were relying on FailUnimplemented, which is untrappable at EL2 (except for HCR_EL2.TGE) since it is just raising Undefined Instruction. Change-Id: I923cb914658ca958af031612cf005159707b0b4f Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/13779 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-10-26arch-arm: Refactor AArch64 MSR/MRS trappingGiacomo Travaglini
This patch refactors AArch64 MSR/MRS trapping, by moving the trapping helpers in arch/arm/utility and in the isa code into a MiscRegOp64 class. This class is the Base class for a generic AArch64 instruction which is making use of system registers (MiscReg), like MSR,MRS,SYS. The common denominator or those instruction is the chance that the system register access is trapped to an upper Exception level. MiscRegOp64 is providing that feature. What do we gain? Other "pseudo" instructions, like access to implementation defined registers can inherit from this class to make use of the trapping functionalities even if there is no data movement between GPRs and system register. Change-Id: I0924354db100de04f1079a1ab43d4fd32039e08d Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/13778 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-10-26arch-arm: Trap to EL2 only if not in Secure StateGiacomo Travaglini
MRS/MSR Instructions should trap to EL2 only if we are in non-Secure state since at the current implementation (Armv8.0) there is no Secure EL2. Change-Id: I93af415fbcbd19a470752adf6afc92e520e9645d Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/13777 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-10-26arch-arm: Fix HVC trapping beahviourGiacomo Travaglini
This patch is fixing HVC trapping behaviour, reusing the pseudocode implementation provided in the arm arm. Change-Id: I0bc81478400b99d84534c1c8871f894722f547c5 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/13776 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-10-26arch-arm: CPTR_EL3.TCPAC traps EL2 accesses to CPACR_EL1Giacomo Travaglini
According to the arm arm, CPTR_EL3.TCPAC traps EL2 accesses to the CPTR_EL2 or HCPTR, and EL2 and EL1 accesses to the CPACR_EL1 or CPACR, are trapped to EL3, unless they are trapped by CPTR_EL2.TCPAC. Change-Id: I637be35b29db39f044dda0c6cc4fe986c9620371 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/13775 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-10-26tests: Convert AddrRangeMap unit test to a GTestAndreas Sandberg
Change-Id: Ifeb0b57c0cda77706691286f78325e50edb31c0d Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/13736 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
2018-10-26tests: Convert CircleBuf unit test to a GTestAndreas Sandberg
Change-Id: I028c6b8d8e0ec06cac3d636689ae647f717096cd Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/13735 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
2018-10-22mem-cache: Move evictBlock(CacheBlk*, PacketList&) to baseDaniel R. Carvalho
Move evictBlock(CacheBlk*, PacketList&) to base cache, as it is both sub-classes implementations are equal. Change-Id: I80fbd16813bfcc4938fb01ed76abe29b3f8b3018 Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br> Reviewed-on: https://gem5-review.googlesource.com/c/13656 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2018-10-19config: add --param to fs.py, se.py and fs_bigLITTLE.pyCiro Santilli
The option allows to set SimObject params from the CLI. The existing config scripts have a large number of options that simply set a single SimObject parameter, and many still are not exposed. This commit allows users to pass arbitrary parameters from the command line to prevent the need for this kind of trivial option. Change-Id: Ic4bd36948aca4998d2eaf6369c85d3668efa3944 Reviewed-on: https://gem5-review.googlesource.com/c/12985 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2018-10-19python: Add utility function to override config parametersCiro Santilli
Add a utility method, SimObject.apply_config that can be used to implement SimObject param overrides from the command line. This function provides safe and convenient semantics for CLI assignment: * The override expression is evaluated in a restricted environment. The only global variables are the child objects and params from the root object. * Only params can be overridden. For example, calling methods or setting attributes on SimObjects isn't possible. * Vectors use non-standard list semantics which enable something similar to glob expansion on the shell. For example, setting: root.system.cpu[0:2].numThreads = 2 will override numThreads for cpu 0 and 1 and: root.system.cpus[0,2].numThreads = 2 sets it for cpus 0 and 2. The intention is that the helper method is called to override default values before calling m5.instantiate. Change-Id: I73f99da21d6d8ce1ff2ec8db2bb34338456f6799 Reviewed-on: https://gem5-review.googlesource.com/c/12984 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2018-10-19arm: treat aarch64 hints as NOPs instead of panicCiro Santilli
Change-Id: Ida2a746e6188171bd2e4da92a4efb33fcbaa2b69 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/13476 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-10-19arm: update hint instruction decoding to match ARMv8.5Ciro Santilli
This fixes: - unallocated hints that have since been allocated - unallocated and unimplemented hint instructions being treated as Unknown instead of the correct NOP - missing encoding for DBG on A32 Unallocated and unimplemented hints give a warning if executed. The most important fix was for the CSDB Spectre mitigation instruction, which was added recently and previously unallocated and treated as Unknown. The Linux kernel v4.18 ARMv7 uses CSDB it and boot would fail with "undefined instruction" since Linux commit 1d4238c56f9816ce0f9c8dbe42d7f2ad81cb6613 Change-Id: I283da3f08a9af4148edc6fb3ca2930cbb97126b8 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/13475 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-10-18mem-cache: Fix unused variable warning in FALRU:invalidate()Nikos Nikoleris
Change-Id: I3b902045433ca56b3e62c251158e784b5fa9e4d7 Signed-off-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/13600 Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
2018-10-18mem: Add write coalescing and write-no-allocate to the cachesNikos Nikoleris
Enable the cache to detect contiguous writes and hold on to the MSHR long enough to allow the entire line to be written. If the whole line is written, the MSHR will be sent out as an invalidation requests, as it is part of a whole-line write, i.e. no-fetch-on-write. The cache is also able to switch to a write-no-allocate policy on the actual completion of the writes, and instead use the tempBlock and turn the write operation into a writeback. These policies are all well-known, and described in works such as Jouppi, Cache Write Policies and Performance, vol 21, no 2, ACM, 1993. Change-Id: I19792f2970b3c6798c9b2b493acdd156897284ae Reviewed-on: https://gem5-review.googlesource.com/c/12907 Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2018-10-18mem: Delay servicing an MSHR after its allocationNikos Nikoleris
An MSHR is allocated and the computed latency determines when the MSHR will be ready and can be serviced by the cache. This patch adds a function that allows changing the time that an MSHR is ready and adjusts the queue such that other MSHRs can be serviced first if they are ready. Change-Id: Ie908191fcb3c2d84d4c6f855c8b1e41ca5881bff Reviewed-on: https://gem5-review.googlesource.com/c/12906 Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2018-10-18mem: Restructure whole-line writes to simplify write mergingNikos Nikoleris
This patch changes how we deal with whole-line writes their responses. With these changes, we use the MSHR tracking to determine if a whole-line is written, and on a fill we simply handle the invalidation response, with the actual writes taking place as part of satisfying the CPU-side hit. Change-Id: I9a18e41a95db3c20b97f8bca7d95ff33d35a578b Reviewed-on: https://gem5-review.googlesource.com/c/12905 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2018-10-18mem: Determine if an MSHR does a whole-line writeNikos Nikoleris
This patch adds support for determining whether the targets in an MSHR are 1) only writes and 2) whether these writes are effectively a whole-line write. This patch adds the necessary functions in the MSHR to allow for write coalescing in the cache. Change-Id: I2c9a9a83d2d9b506a491ba5b0b9ac1054bdb31b4 Reviewed-on: https://gem5-review.googlesource.com/c/12904 Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
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