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AgeCommit message (Expand)Author
2012-01-30MEM: Make the RubyPort physMemPort a PioPort instead of M5PortAndreas Hansson
2012-01-30MEM: Clean-up of Functional/Virtual/TranslatingPort remnantsAndreas Hansson
2012-01-29Yet another merge with the main repository.Gabe Black
2012-01-29Implement Ali's review feedback.Gabe Black
2012-01-28Config: Enable O3 CPU and Ruby in FS modeNilay Vaish
2012-01-28X86 Regressions: Update stats due to introduction of TSONilay Vaish
2012-01-28O3 CPU LSQ: Implement TSONilay Vaish
2012-01-28SE/FS: Get rid of the FULL_SYSTEM config option.Gabe Black
2012-01-28SE/FS: Pull FULL_SYSTEM out of the build_opts filesGabe Black
2012-01-28SE/FS: Get rid of FULL_SYSTEM in the configs directoryGabe Black
2012-01-28SE/FS: Make both SE and FS tests available all the time.Gabe Black
2012-01-28SE/FS: Make SE vs. FS mode a runtime parameter.Gabe Black
2012-01-28MIPS: Fix a compiler warning from the eret instruction.Gabe Black
2012-01-28Merge with the main repo.Gabe Black
2012-01-27ns_gige: Fix a missing curly brace in if-statementAndreas Hansson
2012-01-26configs: actually add ARMv7a-like cpu/cache fileRonald Dreslinski
2012-01-26configs: A more realistic configuration of an ARM-like processorRonald Dreslinski
2012-01-25MEM: Fix fs.py by specifying the range size rather than endAndreas Hansson
2012-01-16Merge yet again with the main repository.Gabe Black
2012-01-12Fix memory corruption issue with CopyStringOut()Mitchell Hayenga
2012-01-25stats: Update stats for final tick and memory bandwidth patchesAli Saidi
2012-01-25sim: display final value of curTick in statsAli Saidi
2012-01-25Mem: Add simple bandwidth stats to PhysicalMemoryAli Saidi
2012-01-23Config: Enable using O3 CPU and Ruby in SE modeNilay Vaish
2012-01-23O3, Ruby: Forward invalidations from Ruby to O3 CPUNilay Vaish
2012-01-23MemCmd: Add a command for invalidation requests to LSQNilay Vaish
2012-01-17MEM: Make the bus default port yet another portAndreas Hansson
2012-01-17MEM: Removing the default port peer from Python portsAndreas Hansson
2012-01-17MEM: Make the bus bridge unidirectional and fixed address rangeAndreas Hansson
2012-01-17MEM: Remove the functional ports from the memory systemWilliam Wang
2012-01-17MEM: Separate queries for snooping and address rangesAndreas Hansson
2012-01-17MEM: Remove Port removeConn and MemObject deletePortRefsAndreas Hansson
2012-01-17MEM: Remove the notion of the default portAndreas Hansson
2012-01-17MEM: Simplify ports by removing EventManagerAndreas Hansson
2012-01-17CPU: Moving towards a more general port across CPU modelsAndreas Hansson
2012-01-17MEM: Add port proxies instead of non-structural portsAndreas Hansson
2012-01-17Ruby: Change the access permissions for MOESI hammerAndreas Hansson
2012-01-17Ruby: Change the access permissions for MOESI hammerAndreas Hansson
2012-01-17MEM: Add the system port as a central access pointAndreas Hansson
2012-01-17MEM: Differentiate functional cache accesses from CPU and memoryAndreas Hansson
2012-01-16stats: undo parser change from initparam changeAli Saidi
2012-01-16Alpha: warn_once about broken PAL breakpoints.Steve Reinhardt
2012-01-16debug: fix AllFlags::disable()Steve Reinhardt
2012-01-12inorder: MDU deadlock fixMaximilien Breughe
2012-01-12mips: compatibility between MIPS_SE and cross compiler from CodeSorceryDeyuan Guo
2012-01-12mips: Fix bugs in faults.cc/hh and tlb.cc for MIPS_FSDeyuan Guo
2012-01-12mips: Fix decoder of two float-convert instructionsDeyuan Guo
2012-01-12mips: definition of MIPS64_QNAN in registers.hhDeyuan Guo
2012-01-12PerfectCacheMemory: Remove references to CacheMsgNilay Vaish
2012-01-11Packet: Put back part of the assertAli Saidi