Age | Commit message (Collapse) | Author |
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arch/isa_parser.py:
Fix include path (bitfield.hh -> base/bitfield.hh).
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kernel.cc and kernel.hh moved to kern/tru64
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remove stuff that is ambiguous
Clean up code a bit
arch/alpha/aout_machdep.h:
Add M5 License
docs/stl.hh:
M5 license
base/remote_gdb.cc:
Most of this is mine, so stick in the m5 license
dev/console.hh:
Clean up comments
merge simple() and out() into one function.
dev/console.hh:
dev/console.cc:
m5 license
dev/console.cc:
merge simple and out.
remove dead code
dev/console.cc:
Remove comments that weren't mine.
Clean up code
dev/console.hh:
update names
dev/alpha_console.cc:
use new interface
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someone will resurrect it some day.
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into zizzer.eecs.umich.edu:/y/ehallnor/work/m5
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sim/sim_time.cc:
make this work in OpenBSD
sim/sim_time.hh:
timeval is defined in sys/time.h
base/remote_gdb.cc:
need to include <cstdio> for sprintf
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base/statistics.hh:
need to use explicit path for #includes
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Grouped the Visible Stats Types and commented them.
base/statistics.hh:
Grouped the Visible Stats Types and commented them.
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They are still under revision control though.
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complaining about extra bk dirs). Feel free to request features (or better yet
add them yourself).
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do this again;
if so we can resurrect from archive.
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arch/alpha/alpha_memory.cc:
arch/alpha/alpha_memory.hh:
arch/alpha/arguments.cc:
arch/alpha/arguments.hh:
arch/alpha/ev5.cc:
arch/alpha/ev5.hh:
arch/alpha/fake_syscall.cc:
arch/alpha/faults.cc:
arch/alpha/isa_desc:
arch/alpha/isa_traits.hh:
arch/alpha/osfpal.cc:
arch/alpha/vtophys.cc:
arch/alpha/vtophys.hh:
base/circlebuf.cc:
base/compression/lzss_compression.cc:
base/compression/lzss_compression.hh:
base/cprintf.cc:
base/cprintf.hh:
base/fast_alloc.cc:
base/fifo_buffer.cc:
base/fifo_buffer.hh:
base/hashmap.hh:
base/hostinfo.cc:
base/hostinfo.hh:
base/hybrid_pred.cc:
base/hybrid_pred.hh:
base/inet.cc:
base/inet.hh:
base/inifile.cc:
base/inifile.hh:
base/intmath.cc:
base/loader/aout_object.cc:
base/loader/aout_object.hh:
base/loader/ecoff_object.cc:
base/loader/ecoff_object.hh:
base/loader/elf_object.cc:
base/loader/elf_object.hh:
base/loader/exec_aout.h:
base/loader/exec_ecoff.h:
base/loader/object_file.cc:
base/loader/object_file.hh:
base/loader/symtab.cc:
base/loader/symtab.hh:
base/misc.cc:
base/misc.hh:
base/pollevent.cc:
base/pollevent.hh:
base/random.cc:
base/random.hh:
base/range.hh:
base/remote_gdb.cc:
base/remote_gdb.hh:
base/res_list.hh:
base/sat_counter.cc:
base/sat_counter.hh:
base/sched_list.hh:
base/socket.cc:
base/statistics.cc:
base/statistics.hh:
base/str.cc:
base/trace.cc:
base/trace.hh:
cpu/base_cpu.cc:
cpu/base_cpu.hh:
cpu/exec_context.cc:
cpu/exec_context.hh:
cpu/exetrace.cc:
cpu/exetrace.hh:
cpu/intr_control.cc:
cpu/intr_control.hh:
cpu/memtest/memtest.cc:
cpu/memtest/memtest.hh:
cpu/pc_event.cc:
cpu/pc_event.hh:
cpu/simple_cpu/simple_cpu.cc:
cpu/simple_cpu/simple_cpu.hh:
cpu/static_inst.cc:
cpu/static_inst.hh:
dev/alpha_console.cc:
dev/alpha_console.hh:
dev/console.cc:
dev/console.hh:
dev/disk_image.cc:
dev/disk_image.hh:
dev/etherbus.cc:
dev/etherbus.hh:
dev/etherdump.cc:
dev/etherdump.hh:
dev/etherint.cc:
dev/etherint.hh:
dev/etherlink.cc:
dev/etherlink.hh:
dev/etherpkt.hh:
dev/ethertap.cc:
dev/ethertap.hh:
dev/simple_disk.cc:
dev/simple_disk.hh:
kern/tru64/tru64_syscalls.cc:
kern/tru64/tru64_syscalls.hh:
sim/debug.cc:
sim/eventq.cc:
sim/eventq.hh:
sim/main.cc:
sim/param.cc:
sim/param.hh:
sim/prog.cc:
sim/prog.hh:
sim/serialize.cc:
sim/serialize.hh:
sim/sim_events.cc:
sim/sim_events.hh:
sim/sim_object.cc:
sim/sim_object.hh:
sim/sim_time.cc:
sim/system.cc:
sim/system.hh:
sim/universe.cc:
test/circletest.cc:
test/cprintftest.cc:
test/initest.cc:
test/nmtest.cc:
test/offtest.cc:
test/paramtest.cc:
test/rangetest.cc:
test/stattest.cc:
test/strnumtest.cc:
test/symtest.cc:
test/tokentest.cc:
test/tracetest.cc:
util/tap/tap.cc:
Make include paths explicit.
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extra : convert_revision : 941cbdc591fd4d3d1d9f095cd58fc23dd2d73840
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makefile and
#include changes.
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rename : sim/cache/lzss_compression.cc => base/compression/lzss_compression.cc
rename : sim/cache/lzss_compression.hh => base/compression/lzss_compression.hh
rename : sim/cache/null_compression.hh => base/compression/null_compression.hh
rename : sim/hybrid_pred.cc => base/hybrid_pred.cc
rename : sim/hybrid_pred.hh => base/hybrid_pred.hh
rename : base/aout_object.cc => base/loader/aout_object.cc
rename : base/aout_object.hh => base/loader/aout_object.hh
rename : base/coff_sym.h => base/loader/coff_sym.h
rename : base/coff_symconst.h => base/loader/coff_symconst.h
rename : base/ecoff_object.cc => base/loader/ecoff_object.cc
rename : base/ecoff_object.hh => base/loader/ecoff_object.hh
rename : base/elf_object.cc => base/loader/elf_object.cc
rename : base/elf_object.hh => base/loader/elf_object.hh
rename : base/exec_aout.h => base/loader/exec_aout.h
rename : base/exec_ecoff.h => base/loader/exec_ecoff.h
rename : base/object_file.cc => base/loader/object_file.cc
rename : base/object_file.hh => base/loader/object_file.hh
rename : base/symtab.cc => base/loader/symtab.cc
rename : base/symtab.hh => base/loader/symtab.hh
rename : sim/predictor.hh => base/predictor.hh
rename : sim/sat_counter.cc => base/sat_counter.cc
rename : sim/sat_counter.hh => base/sat_counter.hh
rename : sim/base_cpu.cc => cpu/base_cpu.cc
rename : sim/base_cpu.hh => cpu/base_cpu.hh
rename : sim/exec_context.cc => cpu/exec_context.cc
rename : sim/exec_context.hh => cpu/exec_context.hh
rename : sim/exetrace.cc => cpu/exetrace.cc
rename : sim/exetrace.hh => cpu/exetrace.hh
rename : sim/op_class.hh => cpu/full_cpu/op_class.hh
rename : sim/smt.hh => cpu/full_cpu/smt.hh
rename : sim/inst_seq.hh => cpu/inst_seq.hh
rename : sim/intr_control.cc => cpu/intr_control.cc
rename : sim/intr_control.hh => cpu/intr_control.hh
rename : sim/memtest.cc => cpu/memtest/memtest.cc
rename : sim/memtest.hh => cpu/memtest/memtest.hh
rename : sim/pc_event.cc => cpu/pc_event.cc
rename : sim/pc_event.hh => cpu/pc_event.hh
rename : sim/simple_cpu.cc => cpu/simple_cpu/simple_cpu.cc
rename : sim/simple_cpu.hh => cpu/simple_cpu/simple_cpu.hh
rename : sim/static_inst.cc => cpu/static_inst.cc
rename : sim/static_inst.hh => cpu/static_inst.hh
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don't need -lpthread anymore
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sim/base_cpu.cc:
sim/exec_context.hh:
sim/hybrid_pred.cc:
sim/main.cc:
sim/prog.hh:
sim/sat_counter.cc:
sim/sim_object.cc:
sim/sim_object.hh:
sim/simple_cpu.cc:
old stats begone!
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while converting them to C++
base/intmath.hh:
Add some functions that were previously defined elsewhere in C
base/misc.cc:
Use the C++ version of memUsage, and sort #includes
sim/prog.cc:
Stop using the old macro versions of various functions and use
the new ones defined in intmath.hh
sim/sim_events.cc:
Stop using the old C versions of various functions and use
the new ones defined in hostinfo.hh
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clean up the formatting
make things use templates since this is C++ now.
base/circlebuf.cc:
base/intmath.cc:
base/intmath.hh:
base/range.hh:
base/remote_gdb.cc:
base/statistics.cc:
base/str.cc:
intmath.h -> intmath.hh
base/intmath.hh:
Make this more like C++ by templatizing these functions
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rename : base/intmath.h => base/intmath.hh
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the master bus is in non event mode.
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into zizzer.eecs.umich.edu:/y/ehallnor/work/m5
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Add blocking_buffer.cc/hh to file-moves
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base/res_list.hh:
Don't need to include std_types.hh
sim/exetrace.hh:
Rename std_types.hh to inst_seq.hh
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rename : sim/std_types.hh => sim/inst_seq.hh
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best of both.
base/fifo_buffer.cc:
base/fifo_buffer.hh:
style
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arch/alpha/alpha_memory.cc:
append a blank line
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into zizzer.eecs.umich.edu:/y/ehallnor/work/m5
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Memory hierarchy again
.psrc:
Don't know why this comes up as changed
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