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AgeCommit message (Expand)Author
2011-03-22Ruby: Remove CacheMsg class from SLICCNilay Vaish
2011-03-21This patch makes garnet use the info about active and inactive vnets during a...Tushar Krishna
2011-03-21fix garnet fleible pipelineTushar Krishna
2011-03-21This patch adds the network tester for simple and garnet networks.Tushar Krishna
2011-03-20SLICC: Remove WakeUp* import calls from ast/__init__.pyNilay Vaish
2011-03-19configs: combine ruby_se.py and se.py to avoid all that code duplicationLisa Hsu
2011-03-19enable x86 workloads on se.pyLisa Hsu
2011-03-19se.py: Modify script to make multiprogramming much easier.Lisa Hsu
2011-03-19util: update aggregator to handle x86 checkpoints.Lisa Hsu
2011-03-19Ruby: Convert CacheRequestType to RubyRequestTypeNilay Vaish
2011-03-19Ruby: Convert AccessModeType to RubyAccessModeNilay Vaish
2011-03-19MOESI_hammer: minor fixes to full-bit dirBrad Beckmann
2011-03-19Ruby: dma retry fixBrad Beckmann
2011-03-19RubyPort: minor fixes to trace flag and dprintfsBrad Beckmann
2011-03-19ruby: added useful dma progress dprintfBrad Beckmann
2011-03-19slicc: improved invalid transition messageBrad Beckmann
2011-03-19MOESI_hammer: fixed dma bug with shared dataBrad Beckmann
2011-03-19MOESI_CMP_directory: significant dma bug fixesBrad Beckmann
2011-03-18SLICC: Remove external_type for structuresNilay Vaish
2011-03-18SLICC: Remove the keyword wake_up_dependentsNilay Vaish
2011-03-18SLICC: Remove the keyword wake_up_all_dependentsNilay Vaish
2011-03-18swig: get rid of m5.internal.random module (swig/random.i)Steve Reinhardt
2011-03-18base: disable FastAlloc in debug builds by defaultSteve Reinhardt
2011-03-17Automated merge with ssh://hg@repo.m5sim.org/m5Ali Saidi
2011-03-17ARM: Update stats for the previous changes and add ARM_FS/O3 regression.Ali Saidi
2011-03-17ARM: Add minimal ARM_SE support for m5threads.Chris Emmons
2011-03-17ARM: Fix subtle bug in LDM.Ali Saidi
2011-03-17ARM: Implement the Instruction Set Attribute Registers (ISAR).Ali Saidi
2011-03-17ARM: Identify branches as conditional or unconditional and direct or indirect.Ali Saidi
2011-03-17ARM: Bare metal system should have 256MB of RAM.Ali Saidi
2011-03-17ARM: Fix small bug with VLDM/VSTM instructions.Ali Saidi
2011-03-17ARM: Detect and skip udelay() functions in linux kernel.Ali Saidi
2011-03-17ARM: Allow conditional quiesce instructions.Ali Saidi
2011-03-17Stats: Update the statistics for rfe patch.Ali Saidi
2011-03-17ARM: Fix RFE macrop.Matt Horsnell
2011-03-17ARM: Rename registers used as temporary state by microops.Matt Horsnell
2011-03-17O3: Send instruction back to fetch on squash to seed predecoder correctly.Ali Saidi
2011-03-17O3: Cleanup the commitInfo comm struct.Ali Saidi
2011-03-17ARM: Previous change didn't end up setting instFlags, this does.Ali Saidi
2011-03-17O3: Update regressions for mem block caching change.Ali Saidi
2011-03-17Mem: Fix issue with dirty block being lost when entire block transferred to n...Ali Saidi
2011-03-17O3: Fix unaligned stores when cache blockedAli Saidi
2011-03-17Ruby: minor bugfix, line did not adhere to some macro usage conventions.Lisa Hsu
2011-03-17Ruby: expose a simple mod function in slicc interface.Lisa Hsu
2011-03-17X86: Update the stats for parser on x86 O3.Ali Saidi
2011-03-16X86: Update the stats for gzip on x86 O3.Gabe Black
2011-03-12Regressions: Move the X86_FS regressions to "quick" instead of "long".Gabe Black
2011-03-12Regressions: Make X86_FS run automatically.Gabe Black
2011-03-11SCons: Stop embedding the mercurial revision into the binary.Gabe Black
2011-03-11Gems: Eliminate the now unused GEMS_ROOT scons variable.Gabe Black