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into ewok.(none):/home/gblack/m5/multiarch
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extra : convert_revision : cb6de8d050ac5abb8f61eb5780deeb06e93b1a0c
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arch/sparc/SConscript:
Fixed up the SPARC SConscript to use the name of the SPARC source files.
arch/sparc/linux_process.cc:
Changed the namespace name from SPARCISA to SparcISA.
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extra : convert_revision : c340fbf78200bf7d962e7578a3f2998860224c53
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extra : convert_revision : 70612a3efc877febbff0c8fb9065dea7e1d12cd8
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OSs and architectures.
SConscript:
Added ./libelf as an include search directory. There might be a better spot for this than where I put it.
arch/SConscript:
Combined the linux_process.h and tru64_process.h into process.h. This allows each ISA to support processes from arbitrary OSs.
arch/alpha/SConscript:
Added process.cc as a source file. It provides an implementation of createProcess, which takes an object_file object and creates the appropriate process object, or dies.
base/loader/elf_object.cc:
Actually extract the OS and architecture from the elf file, rather than always guessing Alpha and Linux.
base/loader/object_file.hh:
Added constants for SPARC, MIPS, and Solaris, and changed the include for the Addr type.
sim/process.cc:
Pushed creation of specific process objects into the ISA specific code.
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extra : convert_revision : b4754e7ca8328672d07e1394c4d162e199606b53
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into zeep.eecs.umich.edu:/z/saidi/work/m5.head
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extra : convert_revision : 8f463682e32a457cd9171c63dcec5209cb850b56
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arch/alpha/system*.
SConscript:
dev/alpha_console.cc:
dev/alpha_console.hh:
kern/freebsd/freebsd_system.cc:
kern/freebsd/freebsd_system.hh:
kern/kernel_stats.cc:
kern/linux/linux_system.cc:
kern/linux/linux_system.hh:
kern/tru64/tru64_system.cc:
kern/tru64/tru64_system.hh:
sim/pseudo_inst.cc:
sim/system.cc:
sim/system.hh:
First cut at moving alpha specefic stuff out of /sim/system*
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extra : convert_revision : eba58f537fc04e605af4fc216e184b074a44c8a0
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use Receive side scaling
dev/ns_gige.cc:
dev/ns_gige.hh:
dev/ns_gige_reg.h:
dev/sinic.cc:
dev/sinic.hh:
dev/sinicreg.hh:
add support for setting the RSS flag to notify the driver
to use RSS
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extra : convert_revision : 5f0c11668ae976634b3bf0caad669a9464a4c041
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into ewok.(none):/home/gblack/m5/multiarch
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extra : convert_revision : f6db244a66431dd6b8c5ba251ed02d76cd509cff
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extra : convert_revision : a4f658bfd39b7f1d219ad8929b8f45457f49299f
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MachineCheck and Alignment faults.
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extra : convert_revision : 4b1429ef5c7a11c25e28f2bc868cc1481a08c5d1
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into zeep.eecs.umich.edu:/z/saidi/work/m5.q
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extra : convert_revision : 4855ecfb3de652456a8be413c9e538c91709dcb6
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arch/sparc/linux_process.cc:
Began modifying this file for sparc, and replaced the alpha syscall numbers with the sparc ones.
arch/sparc/linux_process.hh:
Begain modifying this file for sparc.
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extra : convert_revision : b1ed8ac50a35591521c5feaf1ea9c4b8ccc26dc8
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arch/alpha/ev5.cc:
Commented out the intr_post function since it's not used. If this really -is- needed, it should be moved into the fault class.
arch/alpha/faults.cc:
arch/alpha/faults.hh:
Moved the fault invocation code into the fault class fully, and got rid of the need for isA.
cpu/exec_context.cc:
cpu/exec_context.hh:
Removed the trap function from the ExecContext. The faults will execute normally in full system mode, but always panic in syscall emulation mode.
cpu/ozone/cpu.hh:
cpu/simple/cpu.hh:
Changed the execution context executing a fault to a fault executing on the execution context.
sim/faults.cc:
If not in full system mode, trying to invoke a fault causes a panic.
sim/faults.hh:
Removed the isA function.
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extra : convert_revision : 894dc8f0755c8efc4b7ef5a09fb2cf7373042395
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extra : convert_revision : ab0c8ed2e8d7359b353f34b443e84094ca40c5e6
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arch/sparc/linux_process.cc:
arch/sparc/linux_process.hh:
Formatting & doxygen.
arch/sparc/linux_process.cc:
Added some more ioctl commands to ignore.
Set unlink and rename to the new functions.
Ignore setrlimit, times and rt_sigaction.
Should eventually provide a function for times.
arch/sparc/linux_process.cc:
Fixes for Linux emulation:
- stat struct alignment
- osf_{get,set}sysinfo return values
- additional syscall numbers
- initialize $r0 to 0
arch/sparc/linux_process.cc:
arch/sparc/linux_process.hh:
Updated Copyright
arch/sparc/linux_process.cc:
Alphabetize includes.
arch/sparc/linux_process.cc:
Changed all syscalls to use syscall return object
arch/sparc/linux_process.cc:
Removed unecessary constructor call at each return.
arch/sparc/linux_process.cc:
Rename sim/universe.{cc,hh} to root.{cc,hh}.
arch/sparc/linux_process.cc:
shuffle files around for new directory structure
arch/sparc/linux_process.cc:
Remove RCS Id string
arch/sparc/linux_process.cc:
arch/sparc/linux_process.hh:
Update copyright dates and author list
arch/sparc/linux_process.hh:
remove $Id$ string
arch/sparc/linux_process.cc:
Apply patch for syscall emulation provided by Antti Miettinen (apm@brigitte.dna.fi).
arch/sparc/linux_process.cc:
Added the endianness namespace. This may change.
arch/sparc/linux_process.cc:
Replaced the namespace declaration with including arch/alpha/isa_traits.hh
arch/sparc/linux_process.cc:
fixup for bsd hosts. Some headers are included by default which means that
more variables need TGT_ prefixes and there isn't a stat call (everything
is a stat64 call) so we have to work around that a bit
arch/sparc/linux_process.cc:
Add endian conversions to fstat
arch/sparc/linux_process.cc:
fix #if. I wonder why my compiler had no issues
arch/sparc/linux_process.cc:
add endian conversions for fstat functions
arch/sparc/linux_process.cc:
move architecture independent code into kern/linux/linux.(hh|cc)
arch/sparc/linux_process.hh:
Add getDesc function
arch/sparc/linux_process.cc:
Added using directive for AlphaISA namespace
arch/sparc/linux_process.cc:
Add pipeFunc.
arch/alpha/linux_process.cc:
Renamed arch files to remove alpha prefix, and changed alpha_memory.hh and cc to a more accurate tlb.hh and cc
arch/sparc/linux_process.cc:
bk cp ../alpha/linux_process.cc linux_process.cc
arch/sparc/linux_process.hh:
bk cp ../alpha/linux_process.hh linux_process.hh
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extra : convert_revision : a8eca1c5f848383263a2326b0e3cde4bcd85f14b
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extra : convert_revision : b7ab14ac644f6a38c69aaa5372b3002b21f34af0
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directly prevents reference counting from working correctly.
cpu/simple/cpu.cc:
Used the Fault constructor to create an Interrupt fault.
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extra : convert_revision : ec2ef7e3cd04ee9a44628877dc6e770fb907104b
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extra : convert_revision : 182cdec9a4e05f55edff0c6a114844b9ad2ca8db
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This changeset removes a check that prevents quiescing when an
interrupt is pending. *** You should only call quiesce if that
isn't a problem. ***
arch/alpha/isa/decoder.isa:
sim/pseudo_inst.cc:
sim/pseudo_inst.hh:
Add quiesceNs, quiesceCycles, quisceTime and m5panic pseudo ops.
These quiesce for a number of ns, cycles, report how long
we were quiesced for, and panic the simulator respectively.
The latter is added to the panic() function in the console and linux
kernel instead of executing an infinite loop until someone notices.
cpu/exec_context.cc:
cpu/exec_context.hh:
Add a quiesce end event to the execution contexted which upon
executing wakes up a CPU for quiesceCycles/quiesceNs.
util/m5/Makefile:
Make the makefile more reasonable
util/m5/m5.c:
update the m5op executable to use the files from the linux tree
util/m5/m5op.S:
update m5op.S from linux tree
util/m5/m5op.h:
update m5op.h from linux tree
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rename : util/m5/m5op.s => util/m5/m5op.S
extra : convert_revision : 3be18525e811405b112e33f24a8c4e772d15462d
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into zamp.eecs.umich.edu:/z/ktlim2/clean/m5-clean
arch/alpha/ev5.cc:
cpu/o3/regfile.hh:
Hand merge.
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rename : arch/alpha/alpha_memory.cc => arch/alpha/tlb.cc
extra : convert_revision : c941dd2198851398820b38a66471372ed8454891
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--HG--
extra : convert_revision : 84d852e625f754c4414403e8c3e26bda80500d4f
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--HG--
extra : convert_revision : 0fd5ecbba5dc6299dd046926ec27595ca4d97ee7
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into ewok.(none):/home/gblack/m5/multiarch
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extra : convert_revision : 0b3ffc0605c9043d7f5bf6c15f4a3c68846a732a
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into zizzer.eecs.umich.edu:/z/m5/Bitkeeper/multiarch
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extra : convert_revision : 3a3ff8fcf472db385219a00ae434d1f3fea43b18
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arch/alpha/ev5.cc:
Changed c style casts of Faults to dynamic_casts
arch/alpha/faults.cc:
AlphaFault is now an abstract class.
arch/alpha/faults.hh:
AlphaFault is now an abstract class. Also, AlphaMachineCheckFault and AlphaAlignmentFault multiply inherit from both AlphaFault and from MachineCheckFault and AlignmentFault respectively. These classes get their name from the generic classes.
cpu/o3/alpha_cpu_impl.hh:
Changed a c style cast to a dynamic_cast for a Fault
sim/faults.hh:
All generic Fault classes are now abstract. Also, MachineCheckFault and AlignmentFault inherit FaultBase as a virtual base class to help resolve ambiguities when they are multiply inherited in ISA specific classes. The override the isMachineCheckFault and isAlignmentFault functions appropriately, and provide a standard name for these faults.
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extra : convert_revision : 2cb906708e3eaec4a12587484c09e50ed6ef88fc
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the fault. The actual function still resides in the execution context.
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extra : convert_revision : 56e33536cdd9079ace03896b85ea3c84b6eb4e57
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specific classes to prevent instantiation of the generic classes.
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extra : convert_revision : 0378261342df008c2bf6d260295ef21b15f119a8
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extra : convert_revision : deb54cd82db47abb6d9bac76e072f2a4b1c883b2
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into zamp.eecs.umich.edu:/z/ktlim2/clean/m5-clean
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extra : convert_revision : 97c345f0715a347ce34f9cabd994485f30f2e171
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the FPCR, Uniq, lock flag, lock addr, and IPRs.
They are now accessed by calling readMiscReg()/setMiscReg() on the XC. Old IPR accesses are supported by using readMiscRegWithEffect() and setMiscRegWithEffect() (names may change in the future).
arch/alpha/alpha_memory.cc:
Change accesses to IPR to go through the XC.
arch/alpha/ev5.cc:
Change accesses for IPRs to go through the misc regs.
arch/alpha/isa/decoder.isa:
Change accesses to IPRs to go through the misc regs. readIpr() and setIpr() are now changed to calls to readMiscRegWithEffect() and setMiscRegWithEffect().
arch/alpha/isa/fp.isa:
Change accesses to IPRs and Fpcr to go through the misc regs.
arch/alpha/isa/main.isa:
Add support for all misc regs being accessed through readMiscReg() and setMiscReg(). Instead of readUniq and readFpcr, they are replaced by calls with Uniq_DepTag and Fpcr_DepTag passed in as the register index.
arch/alpha/isa_traits.hh:
Change the MiscRegFile to a class that handles all accesses to MiscRegs, which in Alpha include the FPCR, Uniq, Lock Addr, Lock Flag, and IPRs.
Two flavors of accesses are supported: normal register reads/writes, and reads/writes with effect. The latter are basically the original read/write IPR functions, while the former are normal reads/writes.
The lock flag and lock addr registers are added to the dependence tags in order to support being accessed through the misc regs.
arch/alpha/stacktrace.cc:
cpu/simple/cpu.cc:
dev/sinic.cc:
Change accesses to the IPRs to go through the XC.
arch/alpha/vtophys.cc:
Change access to the IPR to go through the XC.
arch/isa_parser.py:
Change generation of code for control registers to use the readMiscReg and setMiscReg functions.
base/remote_gdb.cc:
Change accesses to the IPR to go through the XC.
cpu/exec_context.hh:
Use the miscRegs to access the lock addr, lock flag, and other misc registers.
cpu/o3/alpha_cpu.hh:
cpu/simple/cpu.hh:
Support interface for reading and writing misc registers, which replaces readUniq, readFpcr, readIpr, and their set functions.
cpu/o3/alpha_cpu_impl.hh:
Change accesses to the IPRs to go through the miscRegs.
For now comment out some of the accesses to the misc regs until the proxy exec context is completed.
cpu/o3/alpha_dyn_inst.hh:
Change accesses to misc regs to use readMiscReg and setMiscReg.
cpu/o3/alpha_dyn_inst_impl.hh:
Remove old misc reg accessors.
cpu/o3/cpu.cc:
Comment out old misc reg accesses until the proxy exec context is completed.
cpu/o3/cpu.hh:
Change accesses to the misc regs.
cpu/o3/regfile.hh:
Remove old access methods for the misc regs, replace them with readMiscReg and setMiscReg. They are dummy functions for now until the proxy exec context is completed.
kern/kernel_stats.cc:
kern/system_events.cc:
Have accesses to the IPRs go through the XC.
kern/tru64/tru64.hh:
Have accesses to the misc regs use the new access methods.
--HG--
extra : convert_revision : e32e0a3fe99522e17294bbe106ff5591cb1a9d76
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cc to a more accurate tlb.hh and cc
--HG--
rename : arch/alpha/alpha_linux_process.cc => arch/alpha/linux_process.cc
rename : arch/alpha/alpha_linux_process.hh => arch/alpha/linux_process.hh
rename : arch/alpha/alpha_memory.cc => arch/alpha/tlb.cc
rename : arch/alpha/alpha_memory.hh => arch/alpha/tlb.hh
rename : arch/alpha/alpha_tru64_process.cc => arch/alpha/tru64_process.cc
rename : arch/alpha/alpha_tru64_process.hh => arch/alpha/tru64_process.hh
extra : convert_revision : 9fe6863cc37347d2a6bd716c529b0a4a50b36ea7
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SConscript:
Changed all of the "targetarch" files to be "arch" files
arch/SConscript:
Added all of the remaining targetarch files to isa_switch_hdrs
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extra : convert_revision : a37d18349e27cf92dce12814f21944daa7fe9480
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kern/kernel_stats.cc:
Replaced targetarch with arch/alpha, since osfpal.hh is not a targetarched file.
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extra : convert_revision : 24a25f27e5912cb949568cf5fd0ab856771ba0d1
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fault base class, and replaced the isA templated function with them where appropriate.
arch/alpha/ev5.cc:
cpu/simple/cpu.cc:
Changed from the isA templated function to isMachineCheckFault and isAlignmentFault
sim/faults.hh:
Added isMachineCheckFault and isAlignmentFault virtual functions to the fault base class.
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extra : convert_revision : 3bf3a4369bc24a039648ee4f2a9c1663362ff2e2
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--HG--
extra : convert_revision : d9586bb8ffaab74673aa0b3d17bb676b949ff212
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than being created directly.
arch/alpha/alpha_memory.cc:
cpu/base_dyn_inst.cc:
dev/alpha_console.cc:
dev/pcidev.hh:
dev/sinic.cc:
MachineCheckFaults are now generated by the ISA, rather than being created directly.
--HG--
extra : convert_revision : 34a7da41639e93be21ed70dac681b27480008d19
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extra : convert_revision : e7ae43d812140ec99b782394e54903153f8d0476
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changed to include targetarch/xxx.hh
cpu/base_dyn_inst.cc:
cpu/o3/bpred_unit.hh:
cpu/o3/comm.hh:
cpu/o3/cpu.hh:
cpu/o3/regfile.hh:
cpu/ozone/cpu_impl.hh:
cpu/ozone/ea_list.cc:
cpu/ozone/ea_list.hh:
kern/kernel_stats.cc:
Changed arch/alpha to targetarch
sim/process.cc:
Changed arch/alpha to targetarch, and removed gaurding ifdef
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extra : convert_revision : 3c29e6baeb1cd900f7b5e11144a5d547a6c7c5ab
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util/stats/stats.py:
fix up a few of the stats.
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extra : convert_revision : 61c600cd146900c8cc0cf60a9036f2e999a5e244
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dev/pktfifo.cc:
add support for copying arbitrary data out of a
packet fifo
dev/pktfifo.hh:
add support for copying arbitrary data out of a
packet fifo.
Add functions to determine where in the fifo a
particular packet is
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extra : convert_revision : f8ddc994ce8577f29af0de3fa418a01e4e2cb0f1
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normal ungrouped barchart
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extra : convert_revision : 7d55440c9bb060607eddbb72448a3413944bb6ba
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util/stats/categories.py:
bit more stuff for categorizing functions
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extra : convert_revision : 03617246a9254a580684dce82836517d1efdfc5b
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util/stats/db.py:
fix usage of hasattr
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extra : convert_revision : b384e1efeda76921c565f9f391694c27273edcec
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util/stats/barchart.py:
clean up some of lisa's messy code
remove trailing whitespace while I'm at it.
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extra : convert_revision : f2fe6777fb4b458fa1d5b5b743f6274014c229ad
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util/stats/chart.py:
add a bool config option for determining
if the legend is inside or outside the figure
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extra : convert_revision : e862d1832a0cc3c1837758cc247bc77c0a02ec12
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util/stats/barchart.py:
Add support for error bars
util/stats/barchart.py:
add support to choose between a legend inside or
outside the figure.
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extra : convert_revision : 14273e385c106bf27a2013991f9f34ca6551b96c
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util/stats/barchart.py:
If there are fewer than 5 colors, pick from a subset of
5 so there is more consistency in colors between graphs
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extra : convert_revision : 6cf64c2f8ed81e714e24a3ebe5a7a60ca168b231
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CPU_MODELS parameter changes.
arch/SConscript:
Fix typo in comment.
cpu/SConscript:
Convert exec signature generator to Action so we can add dependency
on CPU_MODELS environment var.
Print nicer string while we're at it.
Also add some comments.
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extra : convert_revision : bcb38a7941943cf071dac34cdbb2ece5456b8620
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libelf junk.
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extra : convert_revision : 964473c0ff1fc2f8fd9fbb8a1533eb3730b61fac
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and merge it with writeBar0
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extra : convert_revision : 354642e0d528b6a5a7f2cdf0264d93e738b2d4eb
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