gem5 - gem5

Age	Commit message (Expand)	Author
2012-06-03	ISA Parser: Allow predication of source and destination registers	Nilay Vaish
2012-09-11	Ruby: Use uint32_t instead of uint32 everywhere	Nilay Vaish
2012-09-11	Ruby: Use uint8_t instead of uint8 everywhere	Nilay Vaish
2012-09-10	Regression: Updates due to changes to Ruby memory controller	Nilay Vaish
2012-09-10	Ruby System: Convert to Clocked Object	Nilay Vaish
2012-09-10	Ruby Slicc: remove the call to cin.get() function	Nilay Vaish
2012-09-10	Ruby: Bump the stats after recent memory controller changes	Andreas Hansson
2012-09-10	Mem: Allow serializing of more than INT_MAX bytes	Marco Elver
2012-09-10	NetBSD: Build on NetBSD	Palle Lyckegaard
2012-09-10	AddrRange: Remove the unused range_ops header	Andreas Hansson
2012-09-10	Inet: Remove the SackRange and its use	Andreas Hansson
2012-09-10	Device: Update stats for PIO and PCI latency change	Andreas Hansson
2012-09-10	Device: Bump PIO and PCI latencies to more reasonable values	Andreas Hansson
2012-09-09	se.py: support specifying multiple programs via command line	Nilay Vaish
2012-09-07	sim: Update the SimObject documentation	Andreas Sandberg
2012-09-07	sim: Remove the unused SimObject::regFormulas method	Andreas Sandberg
2012-09-07	O3: Get rid of incorrect assert in RAS.	Ali Saidi
2012-09-07	dev: Fix bifield definition in timer_cpulocal.hh	Ali Saidi
2012-09-07	ARM: Fix the compiler and platform identification for building on ARM.	Ali Saidi
2012-09-07	ARM: fix m5 op binary to properly convert 64bit operands	Ali Saidi
2012-09-07	ARM: Fix issue with with way MPIDR is read to include affinity levels.	Matt Evans
2012-09-07	Igbe: Newer kernels seem to allow TSO headers and packet data to be in one desc	Ali Saidi
2012-09-07	CPU: O3-PipeView.py doesn't display the end of timelines.	Djordje Kovacevic
2012-09-07	sim: add validation to make sure there is memory where we're loading the kernel	Krishnendra Nathella
2012-09-07	loader: initialize all memory in the ObjectFile objects.	Ali Saidi
2012-09-07	ARM: Fix one of the timers used in the VExpress EMM platform.	Ali Saidi
2012-09-07	Param: Transition to Cycles for relevant parameters	Andreas Hansson
2012-09-05	stats: Update Ruby regressions for memory controller fix	Joel Hestness
2012-09-05	Ruby Memory Controller: Fix clocking	Joel Hestness
2012-08-28	Ruby: Correct DataBlock =operator	Jason Power
2012-08-28	Clock: Add a Cycles wrapper class and use where applicable	Andreas Hansson
2012-08-28	Clock: Rework clocks to avoid tick-to-cycle transformations	Andreas Hansson
2012-08-28	Port: Stricter port bind/unbind semantics	Andreas Hansson
2012-08-28	Checker: Bump the realview-o3-checker regression	Andreas Hansson
2012-08-28	Checker: Fix checker CPU ports	Andreas Hansson
2012-08-28	swig: Disable unused value warning with llvm 3.1 compilers	Andreas Hansson
2012-08-27	sim: fix overflow check in simulate because Tick is now unsigned	Anthony Gutierrez
2012-08-27	Ruby: remove README.debugging and Decommissioning_note	Nilay Vaish
2012-08-27	System: Remove redundant call to startupCPU	Nilay Vaish
2012-08-27	Ruby: Remove RubyEventQueue	Nilay Vaish
2012-08-27	Ruby Memory Vector: Allow more than 4GB of memory	Nilay Vaish
2012-08-25	Regression: updates ruby.stats due to change in virtual network	Nilay Vaish
2012-08-25	MESI Protocol: Correct the virtual network in profile functions	Nilay Vaish
2012-08-25	MESI Coherence Protocol: Add copyright notice	Nilay Vaish
2012-08-22	DMA: Refactor the DMA device and align timing and atomic	Andreas Hansson
2012-08-22	Packet: Remove NACKs from packet and its use in endpoints	Andreas Hansson
2012-08-22	Bridge: Remove NACKs in the bridge and unify with packet queue	Andreas Hansson
2012-08-22	Port: Extend the QueuedPort interface and use where appropriate	Andreas Hansson
2012-08-21	Device: Remove overloaded pio_latency parameter	Andreas Hansson
2012-08-21	CPU: Remove overloaded function_trace_start parameter	Andreas Hansson