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2011-04-28network: convert links & switches to first class C++ SimObjectsBrad Beckmann
This patch converts links and switches from second class simobjects that were virtually ignored by the networks (both simple and Garnet) to first class simobjects that directly correspond to c++ ojbects manipulated by the topology and network classes. This is especially true for Garnet, where the links and switches directly correspond to specific C++ objects. By making this change, many aspects of the Topology class were simplified. --HG-- rename : src/mem/ruby/network/Network.cc => src/mem/ruby/network/BasicLink.cc rename : src/mem/ruby/network/Network.hh => src/mem/ruby/network/BasicLink.hh rename : src/mem/ruby/network/Network.cc => src/mem/ruby/network/garnet/fixed-pipeline/GarnetLink_d.cc rename : src/mem/ruby/network/Network.hh => src/mem/ruby/network/garnet/fixed-pipeline/GarnetLink_d.hh rename : src/mem/ruby/network/garnet/fixed-pipeline/GarnetNetwork_d.py => src/mem/ruby/network/garnet/fixed-pipeline/GarnetLink_d.py rename : src/mem/ruby/network/garnet/fixed-pipeline/GarnetNetwork_d.py => src/mem/ruby/network/garnet/fixed-pipeline/GarnetRouter_d.py rename : src/mem/ruby/network/Network.cc => src/mem/ruby/network/garnet/flexible-pipeline/GarnetLink.cc rename : src/mem/ruby/network/Network.hh => src/mem/ruby/network/garnet/flexible-pipeline/GarnetLink.hh rename : src/mem/ruby/network/garnet/fixed-pipeline/GarnetNetwork_d.py => src/mem/ruby/network/garnet/flexible-pipeline/GarnetLink.py rename : src/mem/ruby/network/garnet/fixed-pipeline/GarnetNetwork_d.py => src/mem/ruby/network/garnet/flexible-pipeline/GarnetRouter.py
2011-04-28garnet: cleaned up flexible network header fileBrad Beckmann
2011-04-28ruby: moved topology to the top network directoryBrad Beckmann
Moved the Topology class to the top network directory because it is shared by both the simple and Garnet networks. --HG-- rename : src/mem/ruby/network/simple/Topology.cc => src/mem/ruby/network/Topology.cc rename : src/mem/ruby/network/simple/Topology.hh => src/mem/ruby/network/Topology.hh
2011-04-28ruby: removed dated comment in SimpleNetworkBrad Beckmann
2011-04-28event: fix PythonEventNathan Binkert
order of %includes since they matter for this case
2011-04-25stats: update 20.parser o3 now that it works. realview-o3 works too.Nathan Binkert
2011-04-25base: include types.hh in base/stats/mysql.hhNilay Vaish
Due to certain changes made via changeset 8229, the compilation was failing in certain cases. The compiler pointed to base/stats/mysql.hh for not naming a certain types like uint64_t. To rectify this, base/types.hh is being included in base/stats/mysql.hh.
2011-04-23X86: When decoding a memory only inst, fault on reg encodings, don't assert.Gabe Black
This change makes the decoder figure out if an instruction that only supports memory is using a register encoding and decodes directly to "Unknown" which will behave appropriately. This prevents other parts of the instruction creation process from seeing the mismatch and asserting.
2011-04-22tests: updates for stat name changeNathan Binkert
2011-04-20stats: ensure that stat names are validNathan Binkert
2011-04-20stats: one more name violationNathan Binkert
2011-04-20python: fix another bug from changes to main.pyNathan Binkert
2011-04-20fix some build problems from prior changesetsNathan Binkert
2011-04-20Change default regression build from 'fast' to 'opt'Steve Reinhardt
2011-04-20stats: add user settable separator string for arrayed statsBrad Danofsky
Default is '::', so no visible change unless it is overridden
2011-04-20scons: Allow the build directory live under an EXTRAS directoryBrad Danofsky
2011-04-19tests: update stats for name changesNathan Binkert
2011-04-19stats: rename stats so they can be used as python expressionsNathan Binkert
2011-04-19python: different import for dealing with demandimportNathan Binkert
2011-04-17style: fix all_regions code and remove bogus region typeNathan Binkert
2011-04-17style: remove extra debugging printNathan Binkert
2011-04-17file_types: Make code work in Python 2.4Nathan Binkert
2011-04-15unittest: Make unit tests capable of using swig and python, convert stattestNathan Binkert
2011-04-15python: cleanup python code so stuff doesn't automatically happen at startupNathan Binkert
this allows things to be overridden at startup (e.g. for tests)
2011-04-15scons: make a flexible system for guarding source filesNathan Binkert
This is similar to guards on mercurial queues and they're used for selecting which files are compiled into some given object. We already do something similar, but it's mostly hard coded for the m5 binary and the m5 library and I'd like to make it more flexible to better support the unittests
2011-04-15trace: reimplement the DTRACE function so it doesn't use a vectorNathan Binkert
At the same time, rename the trace flags to debug flags since they have broader usage than simply tracing. This means that --trace-flags is now --debug-flags and --trace-help is now --debug-help
2011-04-15debug: create a Debug namespaceNathan Binkert
2011-04-15includes: fix up code after sortingNathan Binkert
2011-04-15includes: sort all includesNathan Binkert
2011-04-15style: add sort_includes to the style hookNathan Binkert
2011-04-15style: move style verifiers into classesNathan Binkert
2011-04-15style: add a user interface wrapper classNathan Binkert
makes things work both with mercurial and stand alone with stdio
2011-04-15util: python implementation of a routine that will sort includesNathan Binkert
I didn't realize that the perl version existed when I started this, this version has a lot more features than the previous one since it will sort and separate python, system, and m5 headers in separate groups, it will remove duplicates, it will also convert c headers to stl headers
2011-04-15region: add a utility class for keeping track of regions of some rangeNathan Binkert
This is basically like the range_map stuff in src/base (range already exists in Python). This code is like a set of ranges. I'm using it to keep track of changed lines in source code, but it could be use to keep track of memory ranges and holes in memory regions. It could also be used in memory allocation type stuff. (Though it's not at all optimized.)
2011-04-15SortedDict: add functions for getting ranges of keys, values, itemsNathan Binkert
2011-04-15python: figure out if the m5.internal package exists even with demandimportNathan Binkert
2011-04-13refcnt: Update doxygen commentsNathan Binkert
2011-04-13refcnt: Inline comparison functionsNathan Binkert
2011-04-13main: separate out interact() so it can be used by other functionsNathan Binkert
2011-04-13util: fix the language type functionNathan Binkert
2011-04-12ARM: Fix stats for ARM_SE checkpoint restore fix.Ali Saidi
Register reads/writes done in startup() count against the stats while they don't count if done in initState().
2011-04-10ARM: Fix checkpoint restoration in ARM_SE.Ali Saidi
2011-04-10ARM: Get rid of some comments/todos that no longer apply.Ali Saidi
2011-04-06ruby: fixes to support more types of RubyRequestsBrad Beckmann
2011-04-04ARM: Update stats for default inclusion of CF adapter.Ali Saidi
2011-04-04ARM: Include IDE/CF controller by default in PBX model.Ali Saidi
Frame buffer and boot linux: ./build/ARM_FS/m5.opt configs/example/fs.py --benchmark=ArmLinuxFrameBuf --kernel=vmlinux.touchkit Linux from a CF card: ./build/ARM_FS/m5.opt configs/example/fs.py --benchmark=ArmLinuxCflash --kernel=vmlinux.touchkit Run Android ./build/ARM_FS/m5.opt configs/example/fs.py --benchmark=ArmAndroid --kernel=vmlinux.android Run MP ./build/ARM_FS/m5.opt configs/example/fs.py --benchmark=ArmLinuxCflash --kernel=vmlinux.mp-2.6.38
2011-04-04Sim: Fix Simulation.py to allow more than 1 core for standard switching.Anthony Gutierrez
This patch moves the assignment of testsys.switch_cpus, testsys.switch_cpus_1, switch_cpu_list, and switch_cpu_list1 outside of the for loop so they are assigned only once, after switch_cpus and switch_cpus_1 are constructed.
2011-04-04ARM: Update stats for previous changes.Ali Saidi
2011-04-04ARM: Use CPU local lock before sending load to mem system.Ali Saidi
This change uses the locked_mem.hh header to handle implementing CLREX. It simplifies the current implementation greatly.
2011-04-04ARM: Fix checkpoint restoration into O3 CPU and the way O3 switchCpu works.Ali Saidi
This change fixes a small bug in the arm copyRegs() code where some registers wouldn't be copied if the processor was in a mode other than MODE_USER. Additionally, this change simplifies the way the O3 switchCpu code works by utilizing TheISA::copyRegs() to copy the required context information rather than the adhoc copying that goes on in the CPU model. The current code makes assumptions about the visibility of int and float registers that aren't true for all architectures in FS mode.
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