Age | Commit message (Collapse) | Author |
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Two new parameters for the CPU models, max_loads_any_thread and max_loads_all_threads.
cpu/memtest/memtest.cc:
cpu/memtest/memtest.hh:
Swap out maxReads for the new commited loads model.
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extra : convert_revision : 35031329bbc476122b2203104537a9f8b46addfa
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Changed the default to not use dot to speed testing of documentation for warnings.
We probably don't want to release postint and postext since there is
information about absolute file locations in them.
Doxyfile:
Turn of DOT for local testing.
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added log info
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finally, the right one. so simple, yet path so heinous.
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just complains too much.
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into zizzer.eecs.umich.edu:/y/ehallnor/work/m5
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to specify it.
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use the correct operator
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removed blank line
docs/footer.html:
removed blank line
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lost an i, hehe, in cut and paste
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added blank space
docs/footer.html:
added blank space
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new file
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Mainly removing whitespace at the end of lines.
This will reduce future diffs/conflicts.
Also adding a space after if, while, and for
This was all accomplished with:
#!/usr/bin/perl -pi~
s/[ ]+$//; # there is a space and a tab in the brackets
s/if\(/if (/g;
s/for\(/for (/g;
s/while\(/while (/g;
arch/alpha/alpha_memory.cc:
arch/alpha/alpha_memory.hh:
arch/alpha/arguments.hh:
arch/alpha/ev5.cc:
arch/alpha/fake_syscall.cc:
arch/alpha/isa_traits.hh:
arch/alpha/vtophys.cc:
base/cprintf.cc:
base/cprintf.hh:
base/cprintf_formats.hh:
base/dbl_list.hh:
base/fast_alloc.cc:
base/fast_alloc.hh:
base/hybrid_pred.cc:
base/hybrid_pred.hh:
base/inet.cc:
base/inifile.cc:
base/intmath.cc:
base/intmath.hh:
base/misc.cc:
base/mod_num.hh:
base/pollevent.cc:
base/random.cc:
base/random.hh:
base/range.hh:
base/refcnt.hh:
base/remote_gdb.cc:
base/remote_gdb.hh:
base/res_list.hh:
base/sat_counter.cc:
base/sat_counter.hh:
base/sched_list.hh:
base/compression/lzss_compression.cc:
base/compression/lzss_compression.hh:
base/compression/null_compression.hh:
base/loader/coff_sym.h:
base/loader/coff_symconst.h:
base/loader/ecoff_object.cc:
base/loader/object_file.cc:
base/loader/object_file.hh:
base/loader/symtab.cc:
base/loader/symtab.hh:
base/socket.cc:
base/statistics.cc:
base/statistics.hh:
base/str.cc:
base/str.hh:
base/trace.cc:
base/trace.hh:
cpu/base_cpu.cc:
cpu/base_cpu.hh:
cpu/exec_context.hh:
cpu/exetrace.cc:
cpu/intr_control.hh:
cpu/pc_event.cc:
cpu/pc_event.hh:
cpu/static_inst.hh:
cpu/full_cpu/op_class.hh:
cpu/full_cpu/smt.hh:
cpu/memtest/memtest.cc:
cpu/memtest/memtest.hh:
cpu/simple_cpu/simple_cpu.cc:
cpu/simple_cpu/simple_cpu.hh:
dev/alpha_access.h:
dev/alpha_console.cc:
dev/alpha_console.hh:
dev/console.cc:
dev/console.hh:
dev/disk_image.cc:
dev/disk_image.hh:
dev/etherbus.cc:
dev/etherdump.cc:
dev/etherint.cc:
dev/etherlink.cc:
dev/etherlink.hh:
dev/ethertap.cc:
dev/pcireg.h:
docs/stl.hh:
kern/tru64/dump_mbuf.cc:
kern/tru64/printf.cc:
kern/tru64/tru64_events.cc:
kern/tru64/tru64_system.cc:
kern/tru64/tru64_system.hh:
sim/debug.cc:
sim/eventq.cc:
sim/eventq.hh:
sim/host.hh:
sim/main.cc:
sim/param.cc:
sim/param.hh:
sim/prog.cc:
sim/serialize.cc:
sim/serialize.hh:
sim/sim_events.cc:
sim/sim_object.cc:
sim/sim_time.cc:
sim/sim_time.hh:
sim/system.cc:
test/bitvectest.cc:
test/circletest.cc:
test/initest.cc:
test/lru_test.cc:
test/nmtest.cc:
test/offtest.cc:
test/sized_test.cc:
test/stattest.cc:
test/symtest.cc:
util/tap/tap.cc:
util/term/term.c:
formatting fixes
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better. This changes how the setup script works, but
you don't need to re-run setup.
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into zans.eecs.umich.edu:/z/binkertn/research/m5/latest
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extra : convert_revision : d5ba96b559be93774e82692099675b6d1f525221
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base/intmath.hh:
Don't return -1 in FloorLog2. That's wierd. Assert instead.
If you care about this, you should check for zero yourself.
Create seprate versions for uint32_t, uint64_t, int32_t, and
int64_t. signed vs unsigned so that error checking can be done
correctly. 32 vs 64 for speed.
Finally, fix a little bug in CeilLog2 that will make it return
the correct result for 1.
kern/tru64/tru64_events.cc:
fix #includes
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into zizzer.eecs.umich.edu:/y/sraasch/m5
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extra : convert_revision : 022364d1e5bf2f3b004ba75164580c1a821b16a5
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base/statistics.hh:
Put a commented-out #define for STAT_DEBUG
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cpu/pc_event.cc:
SCCS merged
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test change that is real is SIM:cycle is now gone.
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into zizzer.eecs.umich.edu:/y/ehallnor/work/m5
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extra : convert_revision : 25b46c6ff1be6ea339dcaccce2f2987e4ea0f484
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Trial fix, uint64_T > long
base/hostinfo.cc:
Trial fix, uint64_T > long
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into its own Tru64System object. Also remove the System builder
stuff and create a Tru64System builder. This makes it much
simpler to support more operating systems.
arch/alpha/ev5.cc:
Each system provides its own mechanism for doing a breakpoint.
base/remote_gdb.hh:
#include <map>
cpu/pc_event.cc:
cpu/pc_event.hh:
Separate out System specific PCEvents
cpu/simple_cpu/simple_cpu.cc:
each system provides its own init script
kern/tru64/dump_mbuf.cc:
kern/tru64/printf.cc:
Stick this in a namespace
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extra : convert_revision : 9f74527ed2ff8010431d9aff34357aaecc1fb3f6
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Make /m5/latest read-only as well.
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base/hostinfo.cc:
Since we're talking about a u_int64, use %lld.
Maybe this should be converted using toNumber in the future.
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Only run on incoming pushes
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arch/alpha/isa_desc:
arch/alpha/isa_traits.hh:
cpu/static_inst.hh:
CPU -> FullCPU
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There is still one documentation warning in the stat code, probably a
doxygen error.
base/statistics.cc:
Added documentation to SubData and StatData.
base/statistics.hh:
Documented most of the basic stats (storage, implemenation) and all of the
visible stats. There is more to be documented, but I'm going crazy now.
Also fixed the DistStor::zero() function to meet the semantics of the other ones.
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the script that generates it.
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arch/alpha/isa_desc:
Fix include: cpu.hh renamed to full_cpu.hh
cpu/pc_event.cc:
Didn't need cpu.hh, just base_cpu.hh.
sim/sim_events.cc:
Didn't need cpu.hh, just param.hh.
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extra : convert_revision : 2e3fd36476c639af950ba2113f67e8ea24c22be8
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arch/isa_parser.py:
Fix include path (bitfield.hh -> base/bitfield.hh).
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cpu/pc_event.cc:
cpu/pc_event.hh:
Do a quick check to see if there is anything to service
before the function is called
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cpu/exec_context.hh:
dev/alpha_console.cc:
sim/system.cc:
sim/system.hh:
Convert from fixed array to a vector
arch/alpha/arguments.hh:
now that CopyData and CopyString are in vtophys.hh, this
include is not necessary
arch/alpha/vtophys.hh:
Include isa_traits.hh for Addr
cpu/pc_event.cc:
Temporarily get this working while we're changing things
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arch/alpha/arguments.hh:
arch/alpha/arguments.cc:
sort #includes
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