gem5 - gem5

Age	Commit message (Expand)	Author
2010-02-27	Config: Fix fs.py's call to CacheConfig.config_cache.	Gabe Black
2010-02-26	cpu_models: get rid of cpu_models.py and move the stuff into SCons	Nathan Binkert
2010-02-26	isa_parser: Make SCons import the isa_parser	Nathan Binkert
2010-02-26	isa_parser: move the operand map stuff into the ISAParser class.	Nathan Binkert
2010-02-26	isa_parser: move more support functions into the ISAParser class	Nathan Binkert
2010-02-26	isa_parser: move more stuff into the ISAParser class	Nathan Binkert
2010-02-26	isa_parser: move the formatMap and exportContext into the ISAParser class	Nathan Binkert
2010-02-26	isa_parser: Make stack objects class members instead of globals	Nathan Binkert
2010-02-26	isa_parser: add a debug variable that changes how errors are reported.	Nathan Binkert
2010-02-26	isa_parser: Use an exception to flag error	Nathan Binkert
2010-02-26	isa_parser: Move more stuff into the ISAParser class	Nathan Binkert
2010-02-26	isa_parser: move code around to prepare for putting more stuff in the class	Nathan Binkert
2010-02-26	isa_parser: simple fixes, formatting and style	Nathan Binkert
2010-02-26	events: Give EventWrapped a default name and description	Nathan Binkert
2010-02-25	configs: pull out cache configuration code from se.py and fs.py.	Lisa Hsu
2010-02-25	stats: update stats for the changes I pushed re: shared cache occupancy	Lisa Hsu
2010-02-24	cache stats: account for writebacks and/or device occupancy in the cache.	Lisa Hsu
2010-02-23	cache: Make caches sharing aware and add occupancy stats.	Lisa Hsu
2010-02-23	stats: this makes some fixes to AverageStat and AverageVector.	Lisa Hsu
2010-02-23	cache: pull CacheSet out of LRU so that other tags can use associative sets.	Lisa Hsu
2010-02-20	BaseDynInst: Preserve the faults returned from read and write.	Timothy M. Jones
2010-02-12	O3PCU: Split loads and stores that cross cache line boundaries.	Timothy M. Jones
2010-02-12	BaseDynInst: Make the TLB translation timing instead of atomic.	Timothy M. Jones
2010-02-12	Power ISA: Add an alignment fault to Power ISA and check alignment in TLB.	Timothy M. Jones
2010-02-10	ruby: fixed data block assignment fix	Brad Beckmann
2010-02-10	ruby: Initialize sender in MI_example-dir	Brad Beckmann
2010-02-10	ruby: Fixed slicc to initialize the m_is_blocking flag	Brad Beckmann
2010-02-01	ruby: Added FS support to the simple mesh topology	Brad Beckmann
2010-02-01	ruby: Set default protocol back to MI_example	Brad Beckmann
2010-01-31	merge	Brad Beckmann
2010-01-31	m5: Added PROTOCOL default for regress fix	Brad Beckmann
2010-01-31	inorder: update hello world mips	Korey Sewell
2010-01-31	inorder: vortex alpha regression	Korey Sewell
2010-01-31	inorder: twolf alpha regression	Korey Sewell
2010-01-31	inorder: update hello world alpha	Korey Sewell
2010-01-31	inorder: double delete inst bug	Korey Sewell
2010-01-31	inorder: inst count mgmt	Korey Sewell
2010-01-31	inorder: implement split stores	Korey Sewell
2010-01-31	inorder: implement split loads	Korey Sewell
2010-01-31	inorder: add activity stats	Korey Sewell
2010-01-31	inorder: object cleanup in destructors	Korey Sewell
2010-01-31	inorder: user per-thread dummy insts/reqs	Korey Sewell
2010-01-31	inorder: add execution unit stats	Korey Sewell
2010-01-31	inorder: recvRetry bug fix	Korey Sewell
2010-01-31	inorder-stats: add prereq to basic stat	Korey Sewell
2010-01-31	inorder: ctxt switch stats	Korey Sewell
2010-01-31	inorder: pipeline stage stats	Korey Sewell
2010-01-31	inorder: enforce stage bandwidth	Korey Sewell
2010-01-31	inorder: set thread status'	Korey Sewell
2010-01-31	inorder: add/remove halt/deallocate context respectively	Korey Sewell