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AgeCommit message (Expand)Author
2018-01-12sim: Allow passing a user-defined L2XBar to addTwoLevelCacheHierarchy().Xiaoyu Ma
2018-01-11util/m5: add Android.mkEarl Ou
2018-01-11arch-riscv: Don't crash when printing unknown CSRsAlec Roelke
2018-01-11mem-ruby: Fix wakeup timeouts for the MOESI_CMP_token protocolNikos Nikoleris
2018-01-11mem-ruby: Remove function that maps responses to a DMA engineNikos Nikoleris
2018-01-11mem-ruby: Add support for multiple DMA engines in MESI_Two_LevelNikos Nikoleris
2018-01-11cpu: Make the CPU's TLB parameter a BaseTLB.Gabe Black
2018-01-11arm, power: Make the python TLB simobjects inherit from BaseTLB.Gabe Black
2018-01-11arch,mem: Remove the default value for page size.Gabe Black
2018-01-11arch,mem: Move page table construction into the arch classes.Gabe Black
2018-01-10configs: Fill in the cpu.isa field in etrace_replay.py since no default are p...Chen Zou
2018-01-10style: change C/C++ source permissions to noexecBKP
2018-01-10arch-riscv: Make use of ImmOp's polymorphismAlec Roelke
2018-01-10alpha,arm,mips,power,riscv,sparc,x86,cpu: Get rid of ISA_HAS_DELAY_SLOT.Gabe Black
2018-01-10arch-riscv,sim: Support clone syscall in RISC-VTuan Ta
2018-01-09mem-cache: Prune unnecessary writebacks in exclusive cachesNikos Nikoleris
2018-01-09util: Add the missing wakecpu m5op in X86.Hanhwi Jang
2018-01-09util: resolve m5op name mismatching in m5op headers.Hanhwi Jang
2018-01-09cpu: Use the NotAnInst flag to avoid passing an inst to fetch faults.Gabe Black
2018-01-09cpu: Add a NotAnInst flag to the BaseDynInst class.Gabe Black
2018-01-09cpu, power: Get rid of the remnants of the EA computation insts.Gabe Black
2018-01-09arm: Make translateFunctional override the base implementation.Gabe Black
2018-01-08gpu-compute: call createThreads() on cpu objs in apu_se.pyTony Gutierrez
2018-01-05arch-riscv: Ignore sched_yield syscall in SE modeTuan Ta
2018-01-05sim: Fix a bug in prlimit syscall in SE modeTuan Ta
2018-01-05arch-riscv: Ignore set_robust_list and get_robust_list syscallsTuan Ta
2018-01-05arch-riscv: Add an implementation of set_tid_address syscall in RISCVTuan Ta
2018-01-05arch-riscv: Correct syscall argument reg countAlec Roelke
2018-01-04arch-riscv: Remove "magic" syscall number constantAlec Roelke
2018-01-02config: Handle NULL simobject parameters in read_config.py.Gabe Black
2018-01-02config: Fix parsing AddrRange parameters in read_config.py.Gabe Black
2018-01-02config: Add a --checkpoint-dir argument to read_config.py.Gabe Black
2017-12-23alpha,arm,mips,power,riscv,sparc,x86: Get rid of TheISA::NoopMachInst.Gabe Black
2017-12-23riscv,x86: Stop using the arch Nop machine instruction unnecessarily.Gabe Black
2017-12-22arch,cpu: "virtualize" the TLB interface.Gabe Black
2017-12-22cpu: Use the generic nop static inst instead of decoding the arch version.Gabe Black
2017-12-22cpu: Add a pointer to a generic Nop StaticInst.Gabe Black
2017-12-21arch-arm: Fixed WFE/WFI trapping behaviourGiacomo Travaglini
2017-12-21arch-arm: Hyp routed undef fault need to change its syndromeGiacomo Travaglini
2017-12-21arch-arm: Fix StaticInst encoding() methodGiacomo Travaglini
2017-12-20cpu: Fix exit_gen.cc which used misc.hh instead of logging.hh.Gabe Black
2017-12-19arch-arm: Instruction size methods in StaticInst classGiacomo Travaglini
2017-12-19arch-arm: Change casting type from reinterpret to staticGiacomo Travaglini
2017-12-19cpu-tester: Added ExitGen to TrafficGenRiken Gohil
2017-12-19cpu-tester: Refactoring traffic generators into separate files.Riken Gohil
2017-12-15mem-ruby: Support atomic_noncaching acceses in rubySwapnil Haria
2017-12-14arch-riscv: Define AT_RANDOM properlyAlec Roelke
2017-12-14arch-riscv: Increase maximum stack sizeAlec Roelke
2017-12-14misc: Updates for gcc7.2 for x86Jason Lowe-Power
2017-12-14ext: Upgrade PyBind11 to version 2.2.1Jason Lowe-Power