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2018-10-03systemc: Teach verify.py to ignore two types of errors.Gabe Black
Change-Id: I9e61a034d7f71bc9b1f28cb976ae8b17d6f37612 Reviewed-on: https://gem5-review.googlesource.com/c/12465 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com>
2018-10-03systemc: Mark a test as expected to fail/report an error.Gabe Black
Change-Id: Ia5e22000449e233a079d8ba7d777a3d030138a44 Reviewed-on: https://gem5-review.googlesource.com/c/12464 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com>
2018-10-03systemc: Add some error checks to sc_set_default_time_unit.Gabe Black
Change-Id: I1d21c56d3b39044d91c96c98d242a571c099707c Reviewed-on: https://gem5-review.googlesource.com/c/12463 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com>
2018-10-03systemc: Mark some tests as expected to fail.Gabe Black
One of them, systemc/kernel/sc_time/test07, should fail, but it should fail from an error check and not a floating point exception like it currently does. Change-Id: I8c8f3c0aac5a5061780a248bde5f6de2feeecc8c Reviewed-on: https://gem5-review.googlesource.com/c/12462 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com>
2018-10-03systemc: Implement sc_(g|s)et_time_resolution.Gabe Black
Change-Id: If546bea633e777cdb2b14f47c0d9d50b044b99cf Reviewed-on: https://gem5-review.googlesource.com/c/12461 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com>
2018-10-03systemc: Teach verify.py to ignore a new error.Gabe Black
Change-Id: Id967719803b5b306792c9fe6e6ddd36c36e09a88 Reviewed-on: https://gem5-review.googlesource.com/c/12460 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com>
2018-10-03systemc: Record that one of the tests will report an error.Gabe Black
This test purposefully fails with an error. Change-Id: I305a186ee076ff4e63ee82c69c27ce85dabc8fdd Reviewed-on: https://gem5-review.googlesource.com/c/12459 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com>
2018-10-03systemc: Report an error if n <= 0 in wait(int n).Gabe Black
This is in the spec, and tested by one of the regression tests. Change-Id: I035cfad279be3859242919a95598f191d5d06165 Reviewed-on: https://gem5-review.googlesource.com/c/12458 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com>
2018-10-03systemc: Toggle off clumping methods together in the ready list.Gabe Black
This is totally legal and good for performance, but because some of Accellera's tests depend on processes which can run in any order running in a particular order to reproduce the golden output, it needs to be disabled to pass the tests. This change leaves it as an option which could even be plumbed out in the future to support some sort of "compatibility" mode with the tests. An alternative would be to verify that the tests pass, change the ordering to the alternative (but still correct) order, and then update the reference output. Change-Id: I113a40dec52f8b623253f8a27886b4a0abe89485 Reviewed-on: https://gem5-review.googlesource.com/c/12457 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com>
2018-10-03systemc: Store timed notifications in a list instead of a set.Gabe Black
This has three advantages. First, the data structure doesn't have to try to keep track of whether or not an event is already listed there. Second, it's easier to delete an item by storing an iterator for it when it gets inserted. Third, the ordering of events is not dependent on the arbitrary ordering of the set, it's bsaed on the fixed order the events get added to the list. One part of this change makes ScEvent-s keep track of what list they're on, and handle their own insertion and deletion when they're scheduled or descheduled. A side effect of that is that it's no longer safe to simply use a range based for loop to loop over all of an ScEvent and deschedule all its events or to run then (which deschedules them internally once they execute). That can be avoided by looping until the list is empty, and operating on the first element. As the first element is processed and removed from the list, the next element will become first and will get picked up in the next iteration. Change-Id: Icad51a63f153297c88e65f85d22ac721e6c571d8 Reviewed-on: https://gem5-review.googlesource.com/c/12456 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com>
2018-10-03systemc: Implement sc_fifo::dump and improve sc_fifo::print.Gabe Black
The print function is supposed to print both pending and committed writes, apparently. Accellera's implementation of sc_fifo uses a ring buffer to store the entries and manages a head and tail pointer to keep track of what's full, etc. Their dump function prints that whole buffer using the indexes. When not using a ring buffer, there's no easy way to determine what those indexes should be. Fortunately the test that uses dump never moves away from the base of the ring buffer, so I can get the same effect (which also makes sense on its own) by printing the index into the fifo instead. Change-Id: I50fe049461f6a5e8a55b54eeb2f134d20f0812c6 Reviewed-on: https://gem5-review.googlesource.com/c/12455 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com>
2018-10-03systemc: Implement the << operator for sc_signal.Gabe Black
Change-Id: I16955e58d96d49ec3bba90b73f5a368a245da438 Reviewed-on: https://gem5-review.googlesource.com/c/12454 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com>
2018-10-03systemc: Implement the "event()" style sc_signal methods.Gabe Black
Change-Id: Ia829aef2292ff2d50e14433d5c36a2e15a9de54b Reviewed-on: https://gem5-review.googlesource.com/c/12453 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com>
2018-10-03systemc: Add a "changeStamp" value to the scheduler.Gabe Black
This value is incremented after each delta cycle's evaluate stage and after timed notifications happen. Its value is used by some channels to determine whether certain events happened within the previous update phase to implement the "event()", "posedge()", and "negedge()" functions. Change-Id: I9a73f0b5007dcbb6a74da9d666f28da1930b9d3d Reviewed-on: https://gem5-review.googlesource.com/c/12452 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com>
2018-10-03systemc: Teach verify.py to ignore "In file: *" in test output.Gabe Black
Those lines are sensitive to the paths to the test files and are even redacted in the golden reference output, presumably for that reason. Change-Id: I9fbd94c1b6d9d4e76397e84a4175d326f27b6e4d Reviewed-on: https://gem5-review.googlesource.com/c/12451 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com>
2018-10-03systemc: Adjust some error messages to match Accellera.Gabe Black
Those messages include an error number in the Accellera implementation. Add those numbers to gem5 so it's easier to check against golden reference output for the regression tests. Change-Id: I35054dd187e86a87eb177f4695d61044c58ce262 Reviewed-on: https://gem5-review.googlesource.com/c/12450 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com>
2018-10-03systemc: Make verify.py filter out some error messages.Gabe Black
Some of the details of these messages would be annoying to match exactly, and the error messages in gem5 go to simerr which isn't being checked. Change-Id: If80b124dd99987e205ccaf81d313d35df4191252 Reviewed-on: https://gem5-review.googlesource.com/c/12449 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com>
2018-10-03systemc: Tell verify.py to expect two tests to fail.Gabe Black
These tests purposefully fail when they run, so a return code of 1 should be considered successful. Change-Id: Ia4ef0469ed946d26a767805ca2d0acd734f1aec9 Reviewed-on: https://gem5-review.googlesource.com/c/12448 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com>
2018-10-03systemc: Raise an error when SC_METHOD, etc. is used after starting.Gabe Black
Those mechanisms for creating processes are only allowed before the end of elaboration, or in other words before sc_start is called. Technically the check in Accellera's implementation won't trigger if the simulation is stopped, and we immitate that behavior. Change-Id: I9b8b5bd32f876781b6e0d5c0ee0e09de19bdabc1 Reviewed-on: https://gem5-review.googlesource.com/c/12447 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com>
2018-10-03systemc: Teach verify.py how to expect failing error codes.Gabe Black
Some tests expect to fail. For those tests (and only those tests) we need to tell verify.py that it's ok if their exit status isn't 0. Also if those tests *don't* fail, then that will also be flagged as an error. This is done by adding an expected_returncode file into the test's source directory which holds what the expected return code should be. Change-Id: I239a28e1d98dd3f76b71028660e492f675a0b3cb Reviewed-on: https://gem5-review.googlesource.com/c/12446 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com>
2018-10-03systemc: Keep track of more cases when we should be ready after resume.Gabe Black
If a thread self suspends, it should be marked as ready after resuming. If a process was already ready when suspended, it should also be remarked as ready after resuming. Special care has to be taken in pre-initialization situations so that processes are put on the right lists, and whether a process is tracked is already marked as ready. Change-Id: I15da7d747db591785358d47781297468c5f9fd09 Reviewed-on: https://gem5-review.googlesource.com/c/12445 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com>
2018-10-03systemc: When sensitive to an event finder, find on all interfaces.Gabe Black
When a process is sensitive to an event finder and that finder is attached to a port which is bound to multiple interfaces, the process is supposed to be made sensitive to the event finder function's result when called on each interface, not just the first one. Change-Id: I92312e04e60fab7a7ea51c1ed687edabe9768205 Reviewed-on: https://gem5-review.googlesource.com/c/12444 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com>
2018-10-03systemc: Make Process track whether it's dynamic on its own.Gabe Black
Processes which are created in end_of_elaboration aren't created with sc_spawn but still need to figure out if they're dynamic. Rather than duplicate the check in sc_spawn, this change centralizes it in the Process class itself. Change-Id: I763d5a0fa89a72fbc82346b6ce2eed852ee72524 Reviewed-on: https://gem5-review.googlesource.com/c/12443 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com>
2018-10-03systemc: Track the module who's end_of_elaboration callback we're in.Gabe Black
Change-Id: Ib5fe3232cfea26df0c3396c583fd80da429cbdd5 Reviewed-on: https://gem5-review.googlesource.com/c/12442 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com>
2018-10-03systemc: sc_spawn can create static or dynamic processes.Gabe Black
Their status depends on when sc_spawn is run. Change-Id: I826adf9d5c905687e705642130ca5ad725ce92af Reviewed-on: https://gem5-review.googlesource.com/c/12441 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com>
2018-10-03systemc: Improve handling of empty process handles.Gabe Black
Most had checks, but didn't print any message. throw_it needed a check as well. Change-Id: I916c837112f9b27852583f01b3e16a6f53d5e7ca Reviewed-on: https://gem5-review.googlesource.com/c/12440 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com>
2018-10-03systemc: Ensure all objects and events have unique names.Gabe Black
Change-Id: I59b78048849953773b80bb2dac9b834762625331 Reviewed-on: https://gem5-review.googlesource.com/c/12439 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com>
2018-10-03systemc: Make sure children of processes are recorded as such.Gabe Black
The process was treated as the parent of the object, but the object wasn't being installed as a child of the process. Change-Id: I6710f34734835cbeceb3d33e5e37b6f5897c5e30 Reviewed-on: https://gem5-review.googlesource.com/c/12438 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com>
2018-10-03systemc: Clamp the time of events to the present.Gabe Black
If systemc attempts to schedule an event in the past, schedule it for right now instead. Still preserve the difference between delta and timed events. This scheme doesn't really make a lot of sense (why not just disallow scheduling events in the past?) but this will approximate what I think the correct behavior is. What's probably supposed to happen is that events in the past are executed from most past to most present until they catch up with now, and then now advances as normal. Our approach is simpler, but won't preserve ordering between multiple events scheduled in the past. Change-Id: I73c1e581c532530178458f044674613a4f4ea3be Reviewed-on: https://gem5-review.googlesource.com/c/12277 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com>
2018-10-03systemc: Implement support for the default time unit.Gabe Black
This is deprecated, but still used in the tests. Change-Id: I454540e419c53624a37f3d1271cb240415b816b6 Reviewed-on: https://gem5-review.googlesource.com/c/12276 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com>
2018-10-03systemc: Implement most of sc_fifo and its interfaces.Gabe Black
There are still some bugs since the output of the tests don't all match, but more tests pass and fewer abort. Change-Id: I37f84d65c4a8a43357c98282096e39b9401fc1dd Reviewed-on: https://gem5-review.googlesource.com/c/12275 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com>
2018-10-02sim-se: Set ArmProcess64 hwcaps depending on ID regsGiacomo Travaglini
ArmProcess64 needs to query AArch64 ID registers to check which hw capability is going to report in the appropriate aux vector's entry. Change-Id: I1e1294b831e902226f9b162f25e841e53b940454 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/13164 Reviewed-by: Brandon Potter <Brandon.Potter@amd.com> Maintainer: Brandon Potter <Brandon.Potter@amd.com>
2018-10-02sim-se: Different HWCAP for ArmProcess32/64Giacomo Travaglini
AArch32 and AArch64 have different HWCAP flags in Linux, but we are currently using AArch32 HWCAP flags to initialize the aux vector of both AArch32 and AArch64 binaries. This patch also fixes a bug that was introduced by running in SE mode a target binary compiled with glibc > 2.18. Using AArch32 flags resulted on CPUID flag being set for AArch64. This incorrectly tells libc that emulation of the midr_el1 is supported. In FullSystem this might work, but since we are in Syscall Emulation there is no OS behind emulating the mrs midr_el1 instruction. By separating AArch32 flags from AArch64 flags we are turning off the CPUID hwcap flag in SE mode. Change-Id: I9f651957ba9d19dc2bc06606de070c6586f0f9fa Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/12884 Reviewed-by: Brandon Potter <Brandon.Potter@amd.com> Maintainer: Brandon Potter <Brandon.Potter@amd.com>
2018-10-02arch-arm: Add FP16 support introduced by Armv8.2-AEdmund Grimley Evans
This changeset adds support for FP/SIMD instructions with half-precision floating-point operands. Change-Id: I4957f111c9c5e5d6a3747fe9d169d394d642fee8 Signed-off-by: Giacomo Gabrielli <giacomo.gabrielli@arm.com> Reviewed-on: https://gem5-review.googlesource.com/13084 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-10-02arch: Fix unserialization of VectorReg valueGabor Dozsa
Change-Id: Iba01ae60e10703877eae299ba924fa1f04a4a387 Signed-off-by: Giacomo Gabrielli <giacomo.gabrielli@arm.com> Reviewed-on: https://gem5-review.googlesource.com/13104 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-10-02arch-arm: Add FP16 support and other primitives to fplibEdmund Grimley Evans
This changeset: - extends fplib to support emulation of half-precision floating-point (FP16) operations; - extends fplib to support additional primitives introduced by the Arm Scalable Vector Extension (SVE) (fplibExpa, fplibScale, fplibTrigMAdd, fplibTrigSMul, fplibTrigSSel); - adds the FZ16 bit to FPSCR; - cleans up fplib code by replacing constants with preprocessor macros and by adding inline functions to recognise NaNs and infinities. Change-Id: If8fdb2a5824b478c8310bbc126ec60cc1105f135 Signed-off-by: Giacomo Gabrielli <giacomo.gabrielli@arm.com> Reviewed-on: https://gem5-review.googlesource.com/13044 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-10-01arch-arm: Implement AArch64 ID regs as bitunionsGiacomo Travaglini
This patch is implementing the following AArch64 ID registers as bitunions, so that it is easier to query for feature availability: - ID_AA64DFR0_EL1 - ID_AA64ISAR0_EL1 - ID_AA64ISAR1_EL1 - ID_AA64MMFR1_EL1 - ID_AA64MMFR2_EL1 - ID_AA64PFR0_EL1 They are updated to the latest Armv8.5 arch release version. RES0 only ID registers like ID_AA64AFR1_EL1 haven't been added. Change-Id: Ied037abe3757421bcfc2834d397a8cf9a2b9f0a7 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/13067 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-10-01arch-arm: Implement AArch64 ID_AA64MMFR2_EL1 registerGiacomo Travaglini
This patch implements AArch64 Memory Model Feature Register 2 (from ARMv8.2) Change-Id: I16d9acaf620fac6d1206e208bd143daec1657daf Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/13066 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-10-01arch-arm: Move MiscReg BitUnions into a separate header fileGiacomo Travaglini
As the number of MiscRegs increases there is the need of a cleaner header file; this patch is separating miscreg.[cc,hh] where the miscreg decoding/utility functions are defined/declared from the MiscReg register types (BitUnion). Change-Id: I815f53b117b50e47f93aa13d78356ef09d2a2541 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/13065 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-10-01arch-arm: Init AArch64 ID registers in SE modeGiacomo Travaglini
One of the auxv vector's flag is the HWCAP, whose bits match the content of several arm ID registers. This patch factors out AArch64 ID registers init into a separate method and creates the symmetric AArch32 ID register init as well, so that we get a meaningful auxiliary vector in SE mode. Change-Id: I52bdb31b67508c4447558ebd7ca743733a69280e Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/13064 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-10-01cpu: Fix typo in header guard for Noncaching cpuGiacomo Travaglini
Change-Id: If8ec5f5f49e99d4989658273723b943dd8df84c6 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/13144 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-10-01dev-arm: Enable FIQ signaling for Group0 interrupts in GICv2Giacomo Travaglini
Change-Id: Iafaf26344a26eade60c08dd2c0d716af14d9b328 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/12948 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-10-01dev-arm: Create postFiq events for GICv2Giacomo Travaglini
GICv2 is signaling IRQs only to the CPU. This patch is adding the capability of scheduling FIQs. Change-Id: I395afc83eb8d58cfd32cd93372bcb6f804364ef5 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/12947 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-10-01dev-arm: Implement GICv2 GICD_IGROUPR registerGiacomo Travaglini
This patch is implementing GICD_IGROUPR register. Change-Id: I1626f61fbf7deec9c81d8d2c135f1d6c0c4eb891 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/12946 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-10-01dev-arm: Fix GICv2 cpu interrupt enable flagGiacomo Travaglini
Read/WriteCpu methods in the GICv2 are accessing the GICC_CTRL register as if writing any non-zero value to the register will enable IRQ signaling to the CPU. Instead, only the 2 least significant bits control group0/group1 enablement. This patch is renaming GICC_CTRL underlying data buffer from cpuEnabled to cpuControl and it is making it an array of uint32_t instead of bool. cpuEnabled now becomes a method and checks if GICC_CTRL.EnableGrp0 or GICC_CTRL.EnableGrp0 are set. Change-Id: I40f0b3c52c40abd482a856f032bf3686f96ef641 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/12945 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-10-01dev-arm: Add basic support for level sensitive SPIs in GICv2Adrien Pesle
For level sensitive interrupt IRQ line must be cleared when interrupt is deasserted. This is not the case for edge-trigerred interrupt. Change-Id: Ib1660da74a296750c0eb9e20878d4ee64bd23130 Reviewed-on: https://gem5-review.googlesource.com/12944 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-10-01sim: Extend (UN)SERIALIZE_ARRAY to BitUnionsGiacomo Travaglini
This patch is making it possible to use SERIALIZE_ARRAY and UNSERIALIZE array for serializing arrays of BitUnions. Change-Id: I682766b472585f70a89338f373fb94dff5db53c3 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/12924 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com>
2018-09-28dev-arm: Make CpuLocalTimer use standard ArmInterruptPinGiacomo Travaglini
Change-Id: I8c4eb9389b47df8cdf1eec966bb2c9da85a7a7c8 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/12744 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-09-28dev-arm: Take into account PPI enable bitGiacomo Travaglini
When checking for PPIs to send to the cpu in the PL390 GIC we were forwarding any pending PPI regardless of their masking in the distributor. Change-Id: I2e294abeca733cca95cd0deeb9659c7d3d9d8734 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/12624 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-09-28arch-arm: raise/clear IRQ when writing to PMOVSCLR/SETGiacomo Travaglini
Writing a 1 to the Overflow Flag Status register should trigger an interrupt raise/clear depending on the register we are currently using (PMOVSCLR for clearing and PMOVSSET for raising). Change-Id: I2091456685a245712045cf7a4932ac36b7dded1d Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/12531 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
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