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2013-01-07config: Reduce DRAM controller regression traffic rateAndreas Hansson
This patch changes the traffic generator period such that it does not completely saturate the DRAM controller and create an ever-growing backlog in the queued port. A separate patch updates the stats.
2013-01-07cpu: Fix the traffic gen read percentageAndreas Hansson
This patch fixes the computation that determines whether to perform a read or a write such that the two corner cases (0 and 100) are both more efficient and handled correctly.
2013-01-07mem: Add sanity check to packet queue sizeAndreas Hansson
This patch adds a basic check to ensure that the packet queue does not grow absurdly large. The queue should only be used to store packets that were delayed due to blocking from the neighbouring port, and not for actual storage. Thus, a limit of 100 has been chosen for now (which is already quite substantial).
2013-01-07ruby: Fix missing cxx_header in SwitchAndreas Hansson
This patch addresses a warning related to the swig interface generation for the Switch class. The cxx_header is now specified correctly, and the header in question has got a few includes added to make it all compile.
2013-01-07scons: Fix libelf linking errors when using clang/llvmAndreas Hansson
This patch fixes a linking error that occurs when using clang/llvm in combination with older versions of glibc. The fix involves adding -std=gnu89 to the command line when compiling libelf as clang defaults to c99, causing issues with the symbols in sysmacros.h being defined multiple times.
2013-01-07config: Replace second keyboard with a mouse.Chris Emmons
The platform has two KMI devices that are both setup to be keyboards. This patch changes the second keyboard to a mouse. This patch will allow keyboard input as usual and additionally provide mouse support.
2013-01-07mem: Fix a bug in the memory serialization file namingAndreas Hansson
This patch fixes a bug that caused multiple systems to overwrite each other physical memory. The system name is now included in the filename such that this is avoided.
2013-01-07arm: Make ID registers ISA parametersAndreas Sandberg
This patch makes the values of ID_ISARx, MIDR, and FPSID configurable as ISA parameter values. Additionally, setMiscReg now ignores writes to all of the ID registers. Note: This moves the MIDR parameter from ArmSystem to ArmISA for consistency.
2013-01-07arch: Make the ISA class inherit from SimObjectAndreas Sandberg
The ISA class on stores the contents of ID registers on many architectures. In order to make reset values of such registers configurable, we make the class inherit from SimObject, which allows us to use the normal generated parameter headers. This patch introduces a Python helper method, BaseCPU.createThreads(), which creates a set of ISAs for each of the threads in an SMT system. Although it is currently only needed when creating multi-threaded CPUs, it should always be called before instantiating the system as this is an obvious place to configure ID registers identifying a thread/CPU.
2013-01-07o3: Fix issue with LLSC ordering and speculationAli Saidi
This patch unlocks the cpu-local monitor when the CPU sees a snoop to a locked address. Previously we relied on the cache to handle the locking for us, however some users on the gem5 mailing list reported a case where the cpu speculatively executes a ll operation after a pending sc operation in the pipeline and that makes the cache monitor valid. This should handle that case by invaliding the local monitor.
2013-01-07cpu: rename the misleading inSyscall to noSquashFromTCAli Saidi
isSyscall was originally created because during handling of a syscall in SE mode the threadcontext had to be updated. However, in many places this is used in FS mode (e.g. fault handlers) and the name doesn't make much sense. The boolean actually stops gem5 from squashing speculative and non-committed state when a write to a threadcontext happens, so re-name the variable to something more appropriate
2013-01-07tests: Always specify memory mode in every test system.Ali Saidi
Previous to this change we didn't always set the memory mode which worked as long as we never attempted to switch CPUs or checked that a CPU was in a memory system with the correct mode. Future changes will make CPUs verify that they're operating in the correct mode and thus we need to always set it.
2013-01-07tests: Create base classes to encapsulate common test configurationsAndreas Sandberg
Most of the test cases currently contain a large amount of duplicated boiler plate code. This changeset introduces a set of classes that encapsulates most of the functionality when setting up a test configuration. The following base classes are introduced: * BaseSystem - Basic system configuration that can be used for both SE and FS simulation. * BaseFSSystem - Basic FS configuration uni-processor and multi-processor configurations. * BaseFSSystemUniprocessor - Basic FS configuration for uni-processor configurations. This is provided as a way to make existing test cases backwards compatible. Architecture specific implementations are provided for ARM, Alpha, and X86.
2013-01-07cache: add note about where conflicts are handledAli Saidi
2013-01-04regressions: stats update due to decoder changesNilay Vaish
2013-01-04Decoder: Remove the thread context get/set from the decoder.Gabe Black
This interface is no longer used, and getting rid of it simplifies the decoders and code that sets up the decoders. The thread context had been used to read architectural state which was used to contextualize the instruction memory as it came in. That was changed so that the state is now sent to the decoders to keep locally if/when it changes. That's significantly more efficient. Committed by: Nilay Vaish <nilay@cs.wisc.edu>
2013-01-04X86: Move address based decode caching in front of the predecoder.Gabe Black
The predecoder in x86 does a lot of work, most of which can be skipped if the decoder cache is put in front of it. Committed by: Nilay Vaish <nilay@cs.wisc.edu>
2013-01-04SPARC: Keep a copy of the current ASI in the decoder.Gabe Black
Committed by: Nilay Vaish <nilay@cs.wisc.edu>
2013-01-04ARM: Keep a copy of the fpscr len and stride fields in the decoder.Gabe Black
Avoid reading them every instruction, and also eliminate the last use of the thread context in the decoders. Committed by: Nilay Vaish <nilay@cs.wisc.edu>
2012-12-30x86 regressions: stats update due to new x87 instructionsNilay Vaish
2012-12-30x86: implement x87 fp instruction fnstswNilay Vaish
This patch implements the fnstsw instruction. The code was originally written by Vince Weaver. Gabe had made some comments about the code, but those were never addressed. This patch addresses those comments.
2012-12-30x86: implement x87 fp instruction fsincosNilay Vaish
This patch implements the fsincos instruction. The code was originally written by Vince Weaver. Gabe had made some comments about the code, but those were never addressed. This patch addresses those comments.
2012-12-12arm regressions: updates to config.ini, terminal filesNilay Vaish
2012-12-12arm: set uopSet_uop as conditional or unconditional controlNathanael Premillieu
uopSet_uop is microop instruction that has the IsControl flags set, but the IsCondControl or IsUncondControl flags seems not to be set, neither in the construction nor where the microop is used. This patch adds the the flags in the constructor of the instruction (MicroUopSetPCCPSR). Committed by: Nilay Vaish <nilay@cs.wisc.edu>
2012-12-12arm: set movret_uop as conditional or unconditional controlNathanael Premillieu
A flag was missing for the movret_uop microop instruction. This patch adds that flag when the instruction is used, not directly in the constructor of the instruction. Committed by: Nilay Vaish <nilay@cs.wisc.edu>
2012-12-11regressions: stats update due to stats from ruby prefetcherNilay Vaish
2012-12-11ruby: add support for prefetching to MESI protocolNilay Vaish
2012-12-11ruby: modify the directed tester to read/write streamsNilay Vaish
The directed tester supports only generating only read or only write accesses. The patch modifies the tester to support streams that have both read and write accesses.
2012-12-11ruby: change slicc to allow for constructor argsNilay Vaish
The patch adds support to slicc for recognizing arguments that should be passed to the constructor of a class. I did not like the fact that an explicit check was being carried on the type 'TBETable' to figure out the arguments to be passed to the constructor. The patch also moves some of the member variables that are declared for all the controllers to the base class AbstractController.
2012-12-11ruby: add a prefetcherNilay Vaish
This patch adds a prefetcher for the ruby memory system. The prefetcher is based on a prefetcher implemented by others (well, I don't know who wrote the original). The prefetcher does stride-based prefetching, both unit and non-unit. It obseves the misses in the cache and trains on these. After the training period is over, the prefetcher starts issuing prefetch requests to the controller.
2012-12-11ruby: add functions for computing next stride/page addressNilay Vaish
2012-12-06regression test: update a couple of config.ini filesNilay Vaish
2012-12-06TournamentBP: Fix some bugs with table sizes and countersErik Tomusk
globalHistoryBits, globalPredictorSize, and choicePredictorSize are decoupled. globalHistoryBits controls how much history is kept, global and choice predictor sizes control how much of that history is used when accessing predictor tables. This way, global and choice predictors can actually be different sizes, and it is no longer possible to walk off the predictor arrays and cause a seg fault. There are now individual thresholds for choice, global, and local saturating counters, so that taken/not taken decisions are correct even when the predictors' counters' sizes are different. The interface for localPredictorSize has been removed from TournamentBP because the value can be calculated from localHistoryBits. Committed by: Nilay Vaish <nilay@cs.wisc.edu>
2012-12-06inorder cpu: add missing DPRINTF argumentMalek Musleh
Committed by: Nilay Vaish <nilay@cs.wisc.edu>
2012-12-06o3 cpu: remove some unused buggy functions in the lsqNathanael Premillieu
Committed by: Nilay Vaish <nilay@cs.wisc.edu>
2012-11-19config: Fix description of checkpoint option from cycle to tickAndreas Hansson
This patch merely updates the description of the "take-checkpoints" option to reflect that it is specified in ticks and not in cycles.
2012-11-16sim: have a curTick per eventqNilay Vaish
This patch adds a _curTick variable to an eventq. This variable is updated whenever an event is serviced in function serviceOne(), or all events upto a particular time are processed in function serviceEvents(). This change helps when there are eventqs that do not make use of curTick for scheduling events.
2012-11-10regressions: stats update due to ruby functional access patchNilay Vaish
2012-11-10ruby: support functional accesses in garnet flexible networkNilay Vaish
2012-11-10ruby: bug in functionalRead, revert recent changesNilay Vaish
Recent changes to functionalRead() in the memory system was not correct. The change allowed for returning data from the first message found in the buffers of the memory system. This is not correct since it is possible that a timing message has data from an older state of the block. The changes are being reverted.
2012-11-08mem: Fix DRAM draining to ensure write queue is emptyAndreas Hansson
This patch fixes the draining of the SimpleDRAM controller model. The controller performs buffering of writes and normally there is no need to ever empty the write buffer (if you have a fast on-chip memory, then use it). The patch adds checks to ensure the write buffer is drained when the controller is asked to do so.
2012-11-03x86, util: add m5_writefile to m5op_x86.SLluis Vilanova
Committed by: Nilay Vaish
2012-11-02ruby: reset and dump stats along with reset of the systemHamid Reza Khaleghzadeh ext:(%2C%20Lluc%20Alvarez%20%3Clluc.alvarez%40bsc.es%3E%2C%20Nilay%20Vaish%20%3Cnilay%40cs.wisc.edu%3E)
This patch adds support to ruby so that the statistics maintained by ruby are reset/dumped when the statistics for the rest of the system are reset/dumped. For resetting the statistics, ruby now provides the resetStats() function that a sim object can provide. As a consequence, the clearStats() function has been removed from RubySystem. For dumping stats, Ruby now adds a callback event to the dumpStatsQueue. The exit callback that ruby used to add earlier is being removed. Created by: Hamid Reza Khaleghzadeh. Improved by: Lluc Alvarez, Nilay Vaish Committed by: Nilay Vaish
2012-11-02mem: fix use after free issue in memories until 4-phase work complete.Ali Saidi
2012-11-02update stats for preceeding changesAli Saidi
2012-11-02mem: Add support for writing back and flushing cachesAndreas Sandberg
This patch adds support for the following optional drain methods in the classical memory system's cache model: memWriteback() - Write back all dirty cache lines to memory using functional accesses. memInvalidate() - Invalidate all cache lines. Dirty cache lines are lost unless a writeback is requested. Since memWriteback() is called when checkpointing systems, this patch adds support for checkpointing systems with caches. The serialization code now checks whether there are any dirty lines in the cache. If there are dirty lines in the cache, the checkpoint is flagged as bad and a warning is printed.
2012-11-02sim: Add drain methods to request additional cleanup operationsAndreas Sandberg
This patch adds the following two methods to the Drainable base class: memWriteback() - Write back all dirty cache lines to memory using functional accesses. memInvalidate() - Invalidate memory system buffers. Dirty data won't be written back. Specifying calling memWriteback() after draining will allow us to checkpoint systems with caches. memInvalidate() can be used to drop memory system buffers in preparation for switching to an accelerated CPU model that bypasses the gem5 memory system (e.g., hardware virtualized CPUs). Note: This patch only adds the methods to Drainable, the code for flushing the TLB and the cache is committed separately.
2012-11-02sim: Add SWIG interface for SerializableAndreas Sandberg
This changeset adds a SWIG interface for the Serializable class, which fixes a warning when compiling the SWIG interface for the event queue. Currently, the only method exported is the name() method.
2012-11-02python: Rename doDrain()->drain() and make it do the right thingAndreas Sandberg
There is no point in exporting the old drain() method in Simulate.py. It should only be used internally by doDrain(). This patch moves the old drain() method into doDrain() and renames doDrain() to drain().
2012-11-02sim: Reuse the code to change memory mode.Andreas Sandberg
changeToAtomic and changeToTiming both do essentially the same thing, they check the type of their input argument, drain the system, and switch to the desired memory mode. This patch moves all of that code to a separate method (changeMemoryMode) and calls that from both changeToAtomic and changeToTiming.
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