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AgeCommit message (Expand)Author
2019-01-22arm: Get rid of some register type definitions.Gabe Black
2019-01-22arm: dev: Replace ArmISA::MiscReg with RegVal in the GIC v3 model.Gabe Black
2019-01-22arch-arm: implement the GDB XML target description for ARMCiro Santilli
2019-01-22ext: import GDB XML target description files for armCiro Santilli
2019-01-22scons: add helpers to access GDB XML description filesCiro Santilli
2019-01-22scons: allow embedding arbitrary blobs into the gem5 executableCiro Santilli
2019-01-22base: add support for GDB's XML architecture definitionCiro Santilli
2019-01-22arch-arm: Move AArch32 IMPLEMENTATION DEFINED registersGiacomo Travaglini
2019-01-22mem: Add tryTiming suppport to CommMonitorSascha Bischoff
2019-01-22sim-se add readv and modifies writevBrandon Potter
2019-01-22sim-se: add ability to get/set sock metadataBrandon Potter
2019-01-22sim-se: add syscalls related to pollingBrandon Potter
2019-01-22sim-se: add calls for network transmissionsBrandon Potter
2019-01-22sim-se: add socket-based functionalityBrandon Potter
2019-01-18base: Fix unitialized storageDaniel R. Carvalho
2019-01-17tests: Fix tests/main.py so it can be run from anywhere.Gabe Black
2019-01-17mem: Allow inserts in the begining of a packet queueNikos Nikoleris
2019-01-17mem: Determine if a packet queue forces ordering at constructionNikos Nikoleris
2019-01-17cpu-o3: Make the smtCommitPolicy a Param.ScopedEnumNikos Nikoleris
2019-01-17cpu-o3: Make the smtROBPolicy a Param.ScopedEnumNikos Nikoleris
2019-01-17cpu-o3: Make the smtIQPolicy a Param.ScopedEnumNikos Nikoleris
2019-01-17cpu-o3: Make the smtLSQPolicy a Param.ScopedEnumNikos Nikoleris
2019-01-17cpu-o3: Make the smtFetchPolicy a Param.ScopedEnumNikos Nikoleris
2019-01-17python: Add support for scoped enumsNikos Nikoleris
2019-01-16cpu: dev: sim: gpu-compute: Banish some ISA specific register types.Gabe Black
2019-01-16arch: Make the ISA register types aliases for the global types.Gabe Black
2019-01-16arm: Make the fp register types 64 bits.Gabe Black
2019-01-16mem-cache: Access Map Pattern Matching PrefetcherJavier Bueno
2019-01-16mem-cache: Signature Path PrefetcherJavier Bueno
2019-01-16mem-cache: allow prefetchers to emit page crossing referencesJavier Bueno
2019-01-16mem-cache: virtual address support for prefetchersJavier Bueno
2019-01-16arch-arm: Read VMPIDR instead of MPIDR when EL2 is EnabledGiacomo Travaglini
2019-01-16arch-arm: Added TLBI_ALL EL2 instructionAnouk Van Laer
2019-01-16arch-riscv: Add interrupt handlingAlec Roelke
2019-01-16arch-riscv: Fix reset function and styleAlec Roelke
2019-01-15cpu: Fix usage of setArchVecElemGiacomo Travaglini
2019-01-15arch-arm: Fix usage of RegId constructor for VecElemGiacomo Travaglini
2019-01-14arm: Stop using the FloatReg and FloatRegBits types.Gabe Black
2019-01-14config: De-nest the code in Port.splice().Gabe Black
2019-01-14config: Fix an error message in Port.splice().Gabe Black
2019-01-11scons: added support of default Python installation on MacOSAndrea Mondelli
2019-01-11misc: updated shabang for python scriptAndrea Mondelli
2019-01-10sim-se, arch-arm: Add support for getdents64Javier Setoain
2019-01-10arch-arm, sim-se: Add support for TLS in cloneAndreas Sandberg
2019-01-10arch-arm, sim-se: Fix incorrect SP handling in cloneAndreas Sandberg
2019-01-10sim-se: Refactor clone to avoid most ifdefsAndreas Sandberg
2019-01-10sim-se: Correctly calculate next PC in cloneAndreas Sandberg
2019-01-10sim-se: Use CONFIG_CLONE_BACKWARDS for ArmAndreas Sandberg
2019-01-10arch-arm, sim-se: Wire up syscalls needed for pthreadsJavier Setoain
2019-01-10dev-arm: Add a VExpress_GEM5_V2 platform with GICv3 supportJairo Balart
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