Age | Commit message (Collapse) | Author |
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minor change to syntax of 'def operands' in ISA descriptions.
arch/alpha/isa/main.isa:
arch/mips/isa/operands.isa:
arch/sparc/isa/operands.isa:
Change 'def operands' statement to work with new
isa_parser changes.
arch/isa_parser.py:
Merge OperandTraits and OperandDescriptor objects into a
unified hierarchy of Operand objects.
Required a change in the syntax of the 'def operands'
statement in the ISA description.
--HG--
extra : convert_revision : cb43f1607311497ead88ba13953d410ab5bc6a37
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arch/isa_parser.py:
Minor cleanup of operand type and traits code:
- build operand size map right away when types are defined
instead of waiting to do it lazily
- check that operand types have been defined before operands
- don't use 'type' as a variable name
- use isinstance() instead of checking for types directly
--HG--
extra : convert_revision : 099c1ee8d490f9c38316749bf87209388c55c971
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instruction format functions in ISA description language.
Take advantage of these features to clean up memory
instruction definitions in Alpha.
arch/alpha/isa/decoder.isa:
arch/alpha/isa/mem.isa:
arch/alpha/isa/pal.isa:
Take advantage of new keyword parameters to disambiguate
instruction vs. memory-request flags, and to provide
a default EA calculation for memory ops (since 99% of them
are the same).
arch/isa_parser.py:
Add two new features to instruction format functions:
- Keyword parameters, a la Python.
- List-valued arguments.
Also export makeList() function to Python code blocks,
as this is handy for dealing with flags.
--HG--
extra : convert_revision : 99bbbaa2e765230aa96b6a06ed193793325f9fb0
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wrong
arch/alpha/alpha_linux_process.cc:
fix #if. I wonder why my compiler had no issues
--HG--
extra : convert_revision : 880a0442b28811db5ec548ce940060d4b26ec634
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arch/alpha/alpha_linux_process.cc:
Add endian conversions to fstat
sim/byteswap.hh:
for some reason I don't understand g++ really wanted a long version defined
even though int32_t should be the same.
--HG--
extra : convert_revision : 5bfe9d3f0b31824fa5a7ae3f51fd0be5ed4d555d
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into pb15.local:/Users/ali/work/m5.head
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into udhcp-macvpn-776.public.engin.umich.edu:/Users/ali/work/m5.head
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arch/alpha/alpha_linux_process.cc:
arch/alpha/alpha_tru64_process.cc:
fixup for bsd hosts. Some headers are included by default which means that
more variables need TGT_ prefixes and there isn't a stat call (everything
is a stat64 call) so we have to work around that a bit
base/intmath.hh:
base/socket.cc:
this is no longer needed with mac os 10.4
cpu/inst_seq.hh:
just use a uint64_t instead of long long
cpu/o3/inst_queue_impl.hh:
I much cleaner way to get max int
sim/syscall_emul.hh:
fix stat64 problems on *BSD
--HG--
extra : convert_revision : 9eef5f896e083ae1774e818a9765dd83e0305942
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Should enable implementation of split-phase timing loads
with new memory model.
May create slight timing differences under FullCPU, as I
believe we were not handling software prefetches correctly
before when the split MemAcc/Exec model was used. I haven't
looked into this in any detail though.
arch/alpha/isa/decoder.isa:
HwLoadStore format split into separate HwLoad and
HwStore formats.
Copy instructions now fall under MiscPrefetch format.
Mem_write_result is now just write_result in store
conditionals.
arch/alpha/isa/mem.isa:
Split MemAccExecute and LoadStoreExecute templates
into separate templates for loads and stores; now
that memory operands are handled differently from
registers, it's impossible to have a single template
serve both.
Also unified the handling of "regular" prefetches
(loads to r31) and "misc" prefetches (e.g., wh64)
under the new scheme. It looks like SW prefetches
were not handled correctly in FullCPU up til now,
since we generated an execute() method for the outer
instruction but didn't generate a proper method for
MemAcc::execute() (instead getting a default no-op
method for that).
arch/alpha/isa/pal.isa:
Split HwLoadStore into separate HwLoad and HwStore
formats to select proper template (see change to
mem.isa in this changeset).
arch/isa_parser.py:
Stop trying to treat memory operands like register
operands, since we never used them in a uniform way
anyway, and it made it impossible to do split-phase
loads as needed for the new CPU model. Now there's no
more 'op_mem_rd', 'op_nonmem_rd', etc.: 'op_rd' just does
register operands, and the template code is responsible
for formulating the call to the memory system. Right now
the only thing exported by InstObjParams is a new attribute
'mem_acc_size' which gives the memory access size in bits,
though more attributes can be added if needed.
Also moved code in findOperands() method to
OperandDescriptorList.__init__(), which is where it belongs.
--HG--
extra : convert_revision : 6d53d07e0c5e828455834ded4395fa40f9146a34
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(thanks to Gabe's include feature!).
arch/alpha/isa/main.isa:
Split out into multiple .isa files.
--HG--
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arch/isa_parser.py:
Clean up ##include code a bit.
arch/sparc/isa/formats.isa:
arch/sparc/isa/main.isa:
Fix include paths.
--HG--
extra : convert_revision : 0689963c2948e5f1088ecbf2cf6018d29bdaceff
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into zizzer.eecs.umich.edu:/z/stever/bk/m5
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into zizzer.eecs.umich.edu:/z/stever/bk/m5
--HG--
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arch/isa_parser.py:
Get rid of "munged name" for operands in C++ code.
That is, "Ra.uq" will now be known in the C++ as "Ra"
rather than "Ra_uq". It wasn't legal to use different
type extensions for the same operand at the same time
anyway, and now it will be easier to refer to explicit
operands in template code if necessary.
--HG--
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into ewok.(none):/home/gblack/m5/multiarch
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into zizzer.eecs.umich.edu:/z/m5/Bitkeeper/multiarch
--HG--
extra : convert_revision : 6b218e875e5c6299cd38727071e401a3e729266a
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arch/sparc/isa/formats.isa:
Changed the file extensions to .isa again.
arch/sparc/isa/main.isa:
Changed the file extensions to .isa again
--HG--
rename : arch/sparc/isa_desc/base.h => arch/sparc/isa/base.isa
rename : arch/sparc/isa_desc/bitfields.h => arch/sparc/isa/bitfields.isa
rename : arch/sparc/isa_desc/decoder.h => arch/sparc/isa/decoder.isa
rename : arch/sparc/isa_desc/formats.h => arch/sparc/isa/formats.isa
rename : arch/sparc/isa_desc/formats/basic.format => arch/sparc/isa/formats/basic.isa
rename : arch/sparc/isa_desc/formats/branch.format => arch/sparc/isa/formats/branch.isa
rename : arch/sparc/isa_desc/formats/integerop.format => arch/sparc/isa/formats/integerop.isa
rename : arch/sparc/isa_desc/formats/mem.format => arch/sparc/isa/formats/mem.isa
rename : arch/sparc/isa_desc/formats/noop.format => arch/sparc/isa/formats/noop.isa
rename : arch/sparc/isa_desc/formats/trap.format => arch/sparc/isa/formats/trap.isa
rename : arch/sparc/isa_desc/includes.h => arch/sparc/isa/includes.isa
rename : arch/sparc/isa_desc/isa_desc => arch/sparc/isa/main.isa
rename : arch/sparc/isa_desc/operands.h => arch/sparc/isa/operands.isa
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into ewok.(none):/home/gblack/m5/multiarch
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extra : convert_revision : 41a0e8c0b2d328bee958126f395369d4549aabfc
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SConscript:
Changed the ISAPath function to take 5 arguments to work with scons 0.97.
--HG--
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instructions
--HG--
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into zazzer.eecs.umich.edu:/z/ksewell/research/m5-sim/m5-multiarch
--HG--
extra : convert_revision : 2bfc19cfa186776ff94440b01ea51f520f61234f
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place ... Edits to Branch Format
arch/mips/isa/decoder.isa:
Code for di,ei,seb,seh,clz,and clo ....
Every instruction has a format now (of course these are initial formats are still subject to change!)
arch/mips/isa/formats/branch.isa:
Format Branch in MIPS similar to Alpha Format
--HG--
extra : convert_revision : 2118a1d9668610b1e9f1dea66d878b7b36c1ac7e
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and file name changes ...
arch/mips/isa/decoder.isa:
add at least BasicOp Format to most if not all instructions
--HG--
rename : arch/mips/isa/formats/basic.format => arch/mips/isa/formats/basic.isa
rename : arch/mips/isa/formats/branch.format => arch/mips/isa/formats/branch.isa
rename : arch/mips/isa/formats/fp.format => arch/mips/isa/formats/fp.isa
rename : arch/mips/isa/formats/int.format => arch/mips/isa/formats/int.isa
rename : arch/mips/isa/formats/mem.format => arch/mips/isa/formats/mem.isa
rename : arch/mips/isa/formats/noop.format => arch/mips/isa/formats/noop.isa
rename : arch/mips/isa/formats/tlbop.format => arch/mips/isa/formats/tlbop.isa
rename : arch/mips/isa/formats/trap.format => arch/mips/isa/formats/trap.isa
rename : arch/mips/isa/mips.isa => arch/mips/isa/main.isa
extra : convert_revision : 0b2f3aee13fee3e0e25c0c746af4216c4a596391
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with isPowerOf2() from intmath.hh.
base/sched_list.hh:
Use isPowerOf2() from intmath.hh.
--HG--
extra : convert_revision : 7b2409531d8ed194aa7e1cfcd1ecb8460c797a16
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--HG--
rename : arch/alpha/isa_desc => arch/alpha/isa/main.isa
extra : convert_revision : a3cc14c202ae606db270c2c29847170d90c05216
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arch/alpha/alpha_linux_process.cc:
arch/alpha/alpha_tru64_process.cc:
Replaced the namespace declaration with including arch/alpha/isa_traits.hh
--HG--
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into ewok.(none):/home/gblack/m5/multiarch
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the isa_desc files, movement of byte_swap.hh into sim, and the creation of arch/isa_traits.hh
SConscript:
Moved some files out of targetarch. The either no longer need to be there, never needed to be there, or should be referred to directly in arch/alpha due to there strictly alpha content.
arch/alpha/isa_traits.hh:
Added alpha's endianness to it's isa_traits.hh
arch/mips/isa_traits.hh:
Added MIPS endianness to it's isa_traits.hh
arch/sparc/isa_traits.hh:
Added SPARCs endianess to it's isa_traits.hh
build/SConstruct:
Added MIPS as a valid architecture
cpu/exec_context.hh:
Included arch/isa_traits.hh to bring in the endianness of the system.
cpu/o3/alpha_cpu.hh:
Included arch/isa_traits.hh to bring in the systems endianness, and removed the hardcoding of little endianness
cpu/o3/fetch_impl.hh:
kern/freebsd/freebsd_system.cc:
Included arch/isa_traits.hh to bring in the systems endianness, and removed the hardcoding to little endianness.
sim/system.cc:
Included arch/isa_traits.hh to bring in the systems endianness, and removed the hardcoding to little endian.
--HG--
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The extra class is needed because of the necessisty of an immediate member variable.
Also, added some 'very modest' python code to choose between the IntOp and
the IntImmOp based on the instruction name ...
--HG--
extra : convert_revision : f109c12418202a99b40e270360134e8335739836
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arch/mips/isa/formats/int.format:
Looks like Integer Ops with Immediates may not need their own separate class because all those instructions are distinct from
their reg-reg counterparts
--HG--
rename : arch/mips/isa/bitfields.def => arch/mips/isa/bitfields.isa
rename : arch/mips/isa/decoder.def => arch/mips/isa/decoder.isa
rename : arch/mips/isa/formats.def => arch/mips/isa/formats.isa
rename : arch/mips/isa/includes.h => arch/mips/isa/includes.isa
rename : arch/mips/isa/operands.def => arch/mips/isa/operands.isa
extra : convert_revision : 8e354b4232b28c0264d98d333d55ef8b5a6589cc
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operations and the majority of the load & store operations (not all of FP-Ops),
Output,Format, & Template code needs to be adjusted to correctly take these "decoder.h" inputs ...
--HG--
extra : convert_revision : 3dcde1f2f587e2766fd61231a93d34d1d7727356
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shift)
arch/mips/isa/bitfields.def:
Add comment, move definition up in file
arch/mips/isa/decoder.def:
add basic arithmetic operations
arch/mips/isa/formats/fp.format:
change Integer -> FP words
arch/mips/isa/formats/int.format:
Add derived IntImm class
arch/mips/isa/operands.def:
change to MIPS sytle operands
--HG--
rename : arch/mips/isa/formats/fpop.format => arch/mips/isa/formats/fp.format
rename : arch/mips/isa/formats/integerop.format => arch/mips/isa/formats/int.format
extra : convert_revision : a95da47bc981e56a9898421da4eeb9c442d1dc15
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--HG--
rename : arch/mips/isa/bitfields.h => arch/mips/isa/bitfields.def
rename : arch/mips/isa/decoder.h => arch/mips/isa/decoder.def
rename : arch/mips/isa/formats.h => arch/mips/isa/formats.def
rename : arch/mips/isa/operands.h => arch/mips/isa/operands.def
extra : convert_revision : 45cb5485311d51982ebcaf1c7eec34e8751c31f5
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--HG--
rename : arch/mips/isa/formats/tlb.format => arch/mips/isa/formats/tlbop.format
extra : convert_revision : 5b1cfba4a5b687c9a271e1a3f67f75e3fa6c2dde
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arch/mips/isa/formats/fpop.format:
Floating Point Formats
arch/mips/isa/formats/tlb.format:
TLB Ops Format
arch/mips/isa/mips.isa:
Name change to mips.isa
--HG--
rename : arch/mips/isa_desc/bitfields.h => arch/mips/isa/bitfields.h
rename : arch/mips/isa_desc/decoder.h => arch/mips/isa/decoder.h
rename : arch/mips/isa_desc/formats.h => arch/mips/isa/formats.h
rename : arch/mips/isa_desc/formats/basic.format => arch/mips/isa/formats/basic.format
rename : arch/mips/isa_desc/formats/branch.format => arch/mips/isa/formats/branch.format
rename : arch/mips/isa_desc/formats/integerop.format => arch/mips/isa/formats/integerop.format
rename : arch/mips/isa_desc/formats/mem.format => arch/mips/isa/formats/mem.format
rename : arch/mips/isa_desc/formats/noop.format => arch/mips/isa/formats/noop.format
rename : arch/mips/isa_desc/formats/trap.format => arch/mips/isa/formats/trap.format
rename : arch/mips/isa_desc/includes.h => arch/mips/isa/includes.h
rename : arch/mips/isa_desc/operands.h => arch/mips/isa/operands.h
extra : convert_revision : 069a24da405b613f688e693fd038ac7a30a4faed
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The new file uses LittleEndianGuest and BigEndianGuest namespaces to allow selecting the appropriate functions.
arch/alpha/alpha_linux_process.cc:
arch/alpha/alpha_tru64_process.cc:
Added the endianness namespace. This may change.
cpu/exec_context.hh:
Changed the include path for byteswap, and forced LittleEndianness for lack of a better solution.
cpu/o3/alpha_cpu.hh:
Forced LittleEndianness, for lack of a better solution.
cpu/o3/alpha_cpu_impl.hh:
Cleared away some commented out code.
cpu/o3/fetch_impl.hh:
Changed the include patch for byteswap, and forced LittleEndianness for lack of a better solution.
cpu/simple/cpu.cc:
Added an include for byteswap.hh, and fixed the SimpleCPU to LittleEndian. This cpu only does alpha, so that's fine.
dev/disk_image.cc:
Changed the include path of byteswap.hh
kern/freebsd/freebsd_system.cc:
kern/linux/linux_system.cc:
Added an include for byteswap.hh, and forced LittleEndianness for lack of a better solution.
sim/system.cc:
Forced LittleEndianness for lack of a better solution.
--HG--
extra : convert_revision : b95d3e1265a825e04bd77622a3ac09fbac6bd206
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into zeep.eecs.umich.edu:/z/saidi/work/m5.multiarch
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into zizzer.eecs.umich.edu:/z/m5/Bitkeeper/multiarch
--HG--
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--HG--
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here, so it has to be defined before the rule to that calls
isa_parser.py
--HG--
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of tabs so using different editors is consistent
util/emacs/m5-c-style.el:
Default to inserting spaces instead of tabs so using different
editors is consistent
--HG--
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--HG--
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--HG--
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arch/mips/isa_desc/formats.h:
arch/mips/isa_desc/formats/basic.format:
arch/mips/isa_desc/formats/branch.format:
arch/mips/isa_desc/formats/integerop.format:
arch/mips/isa_desc/formats/mem.format:
arch/mips/isa_desc/formats/noop.format:
arch/mips/isa_desc/formats/trap.format:
arch/mips/isa_traits.cc:
arch/mips/isa_traits.hh:
changing "sparc" strings to "mips" everywhere
--HG--
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decode it but NOT produce any C++ class object.
All of the code literals are empty as of now. As much as possible instructions were organized into relevant "formats"
and also references to the tables I used from the MIPS manual were noted via appropriate comments.
--HG--
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arch/mips/isa_desc/bitfields.h:
Change from table names to actual bitfield name ...
--HG--
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- this will decode the instructions but not doing anything to create the C++ object yet
(the 1st of many steps!)
arch/mips/isa_desc/bitfields.h:
initial bitfield constants ... copied some from original alpha bitfields
arch/mips/isa_desc/decoder.h:
decoder function skeleton pt.1
- this will decode the instructions but not doing anything to create the C++ object yet
(the 1st of many steps!)
--HG--
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arch/mips/isa_desc/bitfields.h:
arch/mips/isa_desc/formats.h:
arch/mips/isa_desc/formats/basic.format:
arch/mips/isa_desc/formats/branch.format:
arch/mips/isa_desc/formats/integerop.format:
arch/mips/isa_desc/formats/mem.format:
arch/mips/isa_desc/formats/noop.format:
arch/mips/isa_desc/formats/trap.format:
arch/mips/isa_desc/includes.h:
arch/mips/isa_desc/operands.h:
arch/mips/isa_traits.cc:
arch/mips/isa_traits.hh:
copied from sparc ISA directory
arch/mips/isa_desc/decoder.h:
decoder I started to work on...
--HG--
rename : arch/sparc/isa_desc/bitfields.h => arch/mips/isa_desc/bitfields.h
rename : arch/sparc/isa_desc/decoder.h => arch/mips/isa_desc/decoder.h
rename : arch/sparc/isa_desc/formats.h => arch/mips/isa_desc/formats.h
rename : arch/sparc/isa_desc/formats/basic.format => arch/mips/isa_desc/formats/basic.format
rename : arch/sparc/isa_desc/formats/branch.format => arch/mips/isa_desc/formats/branch.format
rename : arch/sparc/isa_desc/formats/integerop.format => arch/mips/isa_desc/formats/integerop.format
rename : arch/sparc/isa_desc/formats/mem.format => arch/mips/isa_desc/formats/mem.format
rename : arch/sparc/isa_desc/formats/noop.format => arch/mips/isa_desc/formats/noop.format
rename : arch/sparc/isa_desc/formats/trap.format => arch/mips/isa_desc/formats/trap.format
rename : arch/sparc/isa_desc/includes.h => arch/mips/isa_desc/includes.h
rename : arch/sparc/isa_desc/operands.h => arch/mips/isa_desc/operands.h
rename : arch/sparc/isa_traits.cc => arch/mips/isa_traits.cc
rename : arch/sparc/isa_traits.hh => arch/mips/isa_traits.hh
extra : convert_revision : d4f281960ecf2dce479fb665469c6f2c5dd3063e
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repository was created.
SConscript:
There is a new SConscript in the arch/alpha directory which has the alpha specific files. To add files for an arch, a similar file should be created.
arch/isa_parser.py:
The isa parser now supports include directives. These are done with ##include
build/SConstruct:
The target directory is passed on so that the architecture specific SConscript can have it. Also, sparc was added as a valid architecture type.
arch/alpha/SConscript:
This SConscript adds the alpha specific source
arch/sparc/isa_desc/operands.h:
This sets up the operand types that the sparc isa uses
arch/sparc/isa_traits.cc:
Implementation of sparc specific things, like a register file with windows
build/build_options/default/SPARC_SE:
The default options for a sparc syscall emulation build.
--HG--
extra : convert_revision : 1afedae61dc8cae0d59d3bf1d41420d929be2efd
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