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2017-11-09mem: Align the snoop behavior in the XBar for atomic and timingNikos Nikoleris
When the XBar receives a Writeback/WriteClean packet, it doesn't need to snoop the upstream caches. It only queries the snoop filter and sets the blockCached flag accordingly. This is in line with the recvTimingReq. Change-Id: I0ae22f21491d75a111019124bb95bac7b16d3cd3 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Anouk Van Laer <anouk.vanlaer@arm.com> Reviewed-on: https://gem5-review.googlesource.com/5043 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2017-11-09arch-arm: Allow dc ivac from EL0 when SCTLR_EL1.UCI=1Nikos Nikoleris
A program running in EL0 is allowed to execute CMOs when the UCI bit in SCTLR is set. The execution of dc ivac, however, would fault uncoditionally when executed from EL0. This change aligns the permission checks for dc ivac with the rest of the CMOs. Change-Id: I1a532f37707c7dc0748b4375252c6ec0bbf95419 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/5058 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2017-11-08dev: Move generic serial devices to src/dev/serialAndreas Sandberg
Change-Id: I104227fc460f8b561e7375b329a541c1fce881b2 Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Curtis Dunham <curtis.dunham@arm.com> Reviewed-on: https://gem5-review.googlesource.com/4291 Reviewed-by: Gabe Black <gabeblack@google.com>
2017-11-08dev: Add a dummy serial deviceAndreas Sandberg
Add a dummy serial device that discards any output and doesn't provide any input. This device can be used to terminate UARTs that don't have a default device (e.g., a terminal) attached. Change-Id: I4a6b0b5037ce360f59bfb5c566e1698d113a1d26 Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Curtis Dunham <curtis.dunham@arm.com> Reviewed-on: https://gem5-review.googlesource.com/4290 Reviewed-by: Gabe Black <gabeblack@google.com>
2017-11-08dev: Refactor UART->Terminal interfaceAndreas Sandberg
The UART models currently assume that they are always wired to a terminal. While true at the moment, this isn't necessarily a valid assumption. This change introduces the SerialDevice class that defines the interface for serial devices. Currently, Terminal is the only class that implements this interface. Change-Id: I74fefafbbaf5ac1ec0d4ec0b5a0f4b246fdad305 Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Curtis Dunham <curtis.dunham@arm.com> Reviewed-on: https://gem5-review.googlesource.com/4289 Reviewed-by: Gabe Black <gabeblack@google.com>
2017-11-07alpha,arm,mips,power,riscv,sparc,x86: Merge exec decl templates.Gabe Black
In the ISA instruction definitions, some classes were declared with execute, etc., functions outside of the main template because they had CPU specific signatures and would need to be duplicated with each CPU plugged into them. Now that the instructions always just use an ExecContext, there's no reason for those templates to be separate. This change folds those templates together. Change-Id: I13bda247d3d1cc07c0ea06968e48aa5b4aace7fa Reviewed-on: https://gem5-review.googlesource.com/5401 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Alec Roelke <ar4jc@virginia.edu> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2017-11-06sim-se: Add prlimit system callAlec Roelke
Some ISAs (namely RISC-V) implement getrlimit and setrlimit using prlimit. This patch adds an implementation for the prlimit system call. Normally prlimit is supposed to provide the functionality of both getrlimit and setrlimit, but because gem5 does not support setrlimit this implementation of prlimit will simply display a warning and return a failure code if the setrlimit mode is used. The same thing will happen if a pid other than 0 is passed to it. Change-Id: I653af2d5a60e716f4d6286196be7600409efcef8 Reviewed-on: https://gem5-review.googlesource.com/5321 Maintainer: Brandon Potter <Brandon.Potter@amd.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
2017-11-02alpha,arm,mips,power,riscv,sparc,x86,isa: De-specialize ExecContexts.Gabe Black
The ISA parser used to generate different copies of exec functions for each exec context class a particular CPU wanted to use. That's since been changed so that those functions take a pointer to the base ExecContext, so the code which would generate those extra functions can be removed, and some functions which used to be templated on an ExecContext subclass can be untemplated, or minimally less templated. Now that some functions aren't going to be instantiated multiple times with different signatures, there are also opportunities to collapse templates and make many instruction definitions simpler within the parser. Since those changes will be less mechanical, they're left for later changes and will probably be done in smaller increments. Change-Id: I0015307bb02dfb9c60380b56d2a820f12169ebea Reviewed-on: https://gem5-review.googlesource.com/5381 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2017-10-31config: Rework the SysPaths functions into functors.Gabe Black
These functions were already being treated as psuedo objects and had properties assigned to them setting what their paths were. That's a bit unusual and made it less obvious what the code was doing, but also forced the "system" function to know what all the possible path searching functions were so that they'd have their "path" property initialized properly in a central location. This change introduces a PathSearcFunc class which encapsulates the mechanisms of the old code and makes it implicitly extensible so that other path searching functions which might look in other directories can be added in other places. Change-Id: I7be28e51481a06ec83997677af99927709b18003 Reviewed-on: https://gem5-review.googlesource.com/5341 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2017-10-31dev: Using Configurable image writer in HDLcdGiacomo Travaglini
The fixed image writer (which was dumping .bmp images only) has been replaced by the configurable one in HDLcd device. Default format is Auto, which gives gem5 the freedom to choose the format it prefers. Change-Id: I0643266556bb10b43cdebd628f6daa2cd5e105dd Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/5183 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2017-10-31vnc: Default image writer type set to AutoGiacomo Travaglini
This commit modifies the default behaviour of the vnc frame dumping process: rather than using 'Bitmap' as a default parameter value, it is using 'Auto'. Auto parameter is letting gem5 to choose the most efficient image format among the available ones. Change-Id: I3c8e2b5a34a5925d24892880ac362dfe38de36e3 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/5182 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2017-10-31base: Introducing utility for writing raw data in png formatGiacomo Travaglini
Originally it was possible to use a Bitmap writer class for dumping a framebuffer snapshot in a .bmp file. This patch enables you to choose another format. In particular it implements the writing of PNG Images using libpng library. The latter has to be already installed in your machine, otherwise gem5 will default to the Bitmap format. This configurable writer has been introduced in the VNC frame dumping mechanism, which is storing changed frame buffers from the VNC server Change-Id: Id7e5763c82235f1ce90381c8486b85a7cce734ce Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/5181 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2017-10-31x86: Fix VEX instruction decoding.Gabe Black
When decoding VEX prefixed instructions, the x86 predecoder wasn't walking past the opcode byte and so was also interpreting it as the modRM byte. Reported-by: likunxi@fas.harvard.edu Change-Id: I6d4bdabfa03411704c48d905c50c7b23072fc615 Reviewed-on: https://gem5-review.googlesource.com/5281 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com>
2017-10-30base: Fix forcing loopback only binding for listeners.Gabe Black
Despite online documentation, the type used for sin_addr.s_addr is not actually an unsigned long, it is an in_addr_t. When an unsigned long is a 64 bit value, the endian conversion moves the relevant bits of the 32 bit in_addr_t to positions which are truncated away. This forces the value to 0 which means to bind to any interface, the opposite of the intended effect. Change-Id: I53c63dea6bd88144dfef1a9a49b478fab30a8ba2 Reviewed-on: https://gem5-review.googlesource.com/5301 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2017-10-20arch-arm: RBIT instruction using mirroring funcGiacomo Travaglini
The high speed bit-reversing function is now used for the Aarch64/32 RBIT instruction implementation. Change-Id: Id5a8a93d928d00fd33ec4061fbb586b8420a1c1b Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/5262 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2017-10-20base: Function for mirroring bits in variable length wordGiacomo Travaglini
This patch introduces a high-speed template function for mirroring the bits (MSB=>LSB) in a variable length word. The function is achieving high performances since it is using a look-up table. Change-Id: Ib0d0480e68d902f25655f74d243de305103eff75 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/5261 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2017-10-20base: Defining make_unique for C++11Giacomo Travaglini
std::make_unique is not available for C++11 compilers, and it has been introduced only in C++14. Since gem5 is not officially supporting the latter at the moment, this patch allows to use it in gem5 if including base/compiler.hh. If compiled under C++14, std::make_unique will be used instead. Change-Id: Ibf1897fad0a1eb1cb0c683cc25170feaa6841997 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/5201 Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2017-10-19cpu-o3: Add M5_VAR_USED to variableJason Lowe-Power
Fixes compile error for gem5.fast on CLANG due to unused variable. Change-Id: Iabe777a27d75ee8bfa7b214fff577aed3c7582c7 Signed-off-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-on: https://gem5-review.googlesource.com/4980 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
2017-10-19scons: Fix the regression tests.Gabe Black
A recent scons cleanup introduced a small bug when setting the variant path of the regression test SConscript. When turned into a relative path, the directory can be interpreted differently depending on what it's considered relative to. When left as a scons node, there is no ambiguity. Change-Id: I162afdc4fcef81db096ec8304f81bc98fa6bf899 Reviewed-on: https://gem5-review.googlesource.com/5221 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Gabe Black <gabeblack@google.com>
2017-10-17scons: Stop generating inc.d in the isa parser.Gabe Black
Generating dependency/build product information in the isa parser breaks scons idea of how a build is supposed to work. Arm twisting it into working forced a lot of false dependencies which slowed down the build. Change-Id: Iadee8c930fd7c80136d200d69870df7672a6b3ca Reviewed-on: https://gem5-review.googlesource.com/5081 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Gabe Black <gabeblack@google.com>
2017-10-17arch-arm: Fix inverted 32/64-bit check in GDBBoris Shingarov
Change-Id: Ided438af19c9b8504d4624119c4d9fb5157c7cf0 Reviewed-on: https://gem5-review.googlesource.com/4720 Reviewed-by: Paul Rosenfeld <prosenfeld@micron.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2017-10-17util: Filter out the For-Upstream commit message tagAndreas Sandberg
Some internal review flows, e.g. the flow used by ARM Research, uses the For-Upstream tag to indicate that a change has been approved for upstream. This tag isn't meaningful outside of the internal review system. Remove it automatically when running the maintainer script to prepare patches to be posted upstream. Change-Id: Ie3745d0e8ad7a1bfddc5ec68ff3e6ff3f91ca8d8 Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Curtis Dunham <curtis.dunham@arm.com> Reviewed-on: https://gem5-review.googlesource.com/5141 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2017-10-13arch-arm: Signal an event when executing store exclusivesNikos Nikoleris
When a store exclusive is executed, whether it is successful or not, the exclusives monitor is cleared and therefore we need to signal an event for the PE. Change-Id: I383c88c769c0ac5f5d36c4b5d39c9681134d3a20 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/4480 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2017-10-13mem: Signal the local monitor when clearing the global monitorNikos Nikoleris
ARM systems require the coordination of the global and local monitors. When the system is run without caches the global monitor is implemented in the abstract memory object. This change adds a callback from the abstract memory that notifies the local monitor when the global monitor is cleared. Additionally, for ARM systems the local monitor signals the event register and wakes the thread context up. Subsequent wait-for-event (WFE) instructions will be immediately signaled. Change-Id: If6c038f3a6bea7239ba4258f07f39c7f9a30500b Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/3760 Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
2017-10-13cpu-o3: Check predication before the SQ size for a debug printNikos Nikoleris
The size of the store entry in the LSQ is used to indicate a fault in the execution of the store. At the same time, a store that is predicated false will also have 0 size in the corresponding store queue entry. This changeset ensures that we check if the store was predicated false before checking the size field. This way we avoid printing stores as faulting when they are only predicated false. Change-Id: Ie07982197bd73d7b44d26a3257d54ecb103a952a Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/4821 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2017-10-13cpu-o3: Avoid early checker verification for store conditionalsNikos Nikoleris
The O3CPU allows stores to commit before they are completed and as soon as they enter the store queue. This is the reason why stores are verified by the the checker CPU, separately, once they complete and after they are sent to the memory. Store conditionals, on the other hand, have an additional writeback stage in the pipeline as they return their result to a register, similarly to loads. This is the reason why they do not commit before they receive a response from the memory. This allows store conditionals to be verified by the checker CPU as soon as they commit in the same way as all other non-store insturctions. At the same time, the presense of a checker CPU should not require changes to way we handle instructions. This change removes explicit calls to: * incorrectly set the extra data of the request to 0 (a subsequent call to completeAcc already does this without making any ISA assumptions about the return value of the failed store conditional) * complete failing store conditionals Change-Id: If21d70b21caa55b35e9fdcc50f254c590465d3c3 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/4820 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2017-10-05tests: Fix path for module imports in ARM system configs againCurtis Dunham
One configuration was missed in "tests: Fix path for module imports in ARM system configs", which this changeset remedies. Change-Id: I705e64298a8251dcfefbdca927d61c9bbb8bbea7 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/4940 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2017-10-05misc: Add util/packet_pb2.py to .gitignore.Gabe Black
This file is automatically generated and not managed by git. Change-Id: I077fe1ad89b65716a829b783a8b9c6e23b4d0b6b Reviewed-on: https://gem5-review.googlesource.com/5006 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2017-10-05misc: Use a Makefile to ensure util/packet_pb2.py is up to date.Gabe Black
Rather than just ensuring that packet_pb2.py is available in general, use a Makefile to ensure that it's also up to date in case packet.proto has changed. Also, remove a check that ensures that the protobuf module is available, since python will complain if it needs it and can't find it. Finally, remove a comment which talks about manually regenerating the packet_pb2.py module, something that hasn't been necessary for a while, even with the old version of this code. Change-Id: I40c5c1f577e6d7ad1af9a209309a1eb92f073317 Reviewed-on: https://gem5-review.googlesource.com/5005 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2017-10-05misc: When building packet_pb2.py, don't assume a particular CWD.Gabe Black
Allow the script to be run from anywhere, and compute the paths relative to where the script is. The script is assumed to be in util. Change-Id: I8500ef959f2ff8119540c956f2b27789c96de60e Reviewed-on: https://gem5-review.googlesource.com/5004 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2017-10-05misc: Make decode_packet_trace.py print the new master ID fields.Gabe Black
Those fields are "repeated" which means they can appear zero times, which they will in older style traces. Change-Id: Ib6ff4aab521332cf1405549d0d6e922c51c12f32 Reviewed-on: https://gem5-review.googlesource.com/5003 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2017-10-05misc: Small style fix in _EncodeVarint32.Gabe Black
Added spaces around the '|' operator. Change-Id: I5cb82b98e7d2769605cde141f76a62a6e3c6570d Reviewed-on: https://gem5-review.googlesource.com/5002 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2017-10-05misc: Rename the (De|En)codeVarint function _(De|En)codeVarint32.Gabe Black
DecodeVarint implicitly truncates its inputs to 32 bits, and that should be obvious from its name, and so not a surprise to the caller. EncodeVarint also has the suffix added for consistency. Both functions are only used in protolib.py, so add a _ to make it private (in the python sense) to the module. Change-Id: I835295717bb51672351b963fe1227ed619836f22 Reviewed-on: https://gem5-review.googlesource.com/5001 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2017-10-05misc: Fix the indentation in DecodeVarint in util/protolib.py.Gabe Black
The DecodeVarint was, as a comment describes, lifted from google.protobuf.internal.decoder. Unfortunately, the relative indentation of some lines was changed, changing what scope they fell under. This changed the behavior of the function, breaking it for multibyte and negative values. This change restores the correct indentation and fixes the function's behavior. Change-Id: If645649506b0fe5a617b37a8202c9ca1c57aaf15 Reviewed-on: https://gem5-review.googlesource.com/5000 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2017-10-04tlm: Elastic Trace Example with L2 Cache AddedMatthias Jung
The SystemC TLM examples already include an example setup for elastic traces. However, in the provided examples the L2 cache is omitted. This patch provides an additionall example, which also includes an L2 cache on the gem5 side. Change-Id: I49e9fa074b60007694abff37663f0400caf72099 Reviewed-on: https://gem5-review.googlesource.com/4900 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Christian Menard <christian.menard@tu-dresden.de> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2017-09-28sim-se: Fix mremap for downward growing mmap regionsRico Amslinger
mremapFunc(...) did not respect Process::mmapGrowsDown(). This resulted in an attempt to remap into an already allocated region and a panic in FuncPageTable::allocate(...). This behavior can be observed in 435.gromacs. Change-Id: Ib3ad33816126c76506d69679bdcefa7a98ef69f9 Reviewed-on: https://gem5-review.googlesource.com/4700 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Brandon Potter <Brandon.Potter@amd.com>
2017-09-27arch-x86: fix CondInst decoding for MOV to Control RegistersBjoern A. Zeeb
MOV Rd,Cd is MR encoded but the control register is operand 2 not operand 1 hence this needs to be MODRM_REG not MODRM_RM. While MOV Cd,Rd is RM encoded registers are also swapped, so it also needs to be MODRM_REG as well (as it already correctly is). This fixes incorrect UD2 reportings leading to invalid traps reported in O3 on X86 FS introduced with 4e939a7 . Change-Id: Ib33c8ba87b00e0264d33da44fff64ed9e4d2d9d8 Reviewed-on: https://gem5-review.googlesource.com/4861 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2017-09-27arch: change panic for Vector traceData to warn_onceBjoern A. Zeeb
Make the traceData panic for Vectors a warn_once. It's a pity it's not implemented but it's not a reason to abort the simulation entirely. Change-Id: I5e97258fd4e3fa385cfe0c4b400524d1f7b154df Reviewed-on: https://gem5-review.googlesource.com/4860 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Gabe Black <gabeblack@google.com>
2017-09-27sim: make compile on FreeBSD prior to 11Bjoern A. Zeeb
FreeBSD before the early 11 development is expecting a char * for stack.ss_sp rather than the standards compliant void *. Catch that case and allow gem5 to compile on old FreeBSD versions. Change-Id: Ic0ae560b52bfe5b3905ae87df791d349e053ec97 Reviewed-on: https://gem5-review.googlesource.com/4660 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2017-09-26util: Make dot_writer ignore NULL simobjects.Gabe Black
Also centralize the code which iterates over the parameters of a simnode's children, and remove a copy/paste block of code in the DVFS block of code. Change-Id: I01305fbff59346010780ee386ba97ad9106b1f5d Reviewed-on: https://gem5-review.googlesource.com/4849 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Gabe Black <gabeblack@google.com>
2017-09-26dev: Make the IDE controller handle NULL simobject pointers.Gabe Black
Only panic if there are disks which would actually be connected to it beyond its limit. Also skip past disks which are set to NULL. This is useful since it lets you set up disks on different ports of the controller instead of filling them contiguously. Change-Id: I92f1316d3ad6931e25bfffeb34fb2603c0b95ce7 Reviewed-on: https://gem5-review.googlesource.com/4848 Maintainer: Gabe Black <gabeblack@google.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
2017-09-26sim: Add a get_config_as_dict to the NullSimObject class.Gabe Black
Change-Id: I1ba6f6b196b7dfa790d1baaa23640bb3ed73f450 Reviewed-on: https://gem5-review.googlesource.com/4847 Maintainer: Gabe Black <gabeblack@google.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
2017-09-26sim: Don't add the NULL SimObject as a child of other SimObjects.Gabe Black
Change-Id: Ibdc48af8e5a461077f75d781cfd8191586c54115 Reviewed-on: https://gem5-review.googlesource.com/4846 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Gabe Black <gabeblack@google.com>
2017-09-26misc: Make the m5 utilities writefile command accept a host path.Gabe Black
When the writefile command is given one command line argument, it's treated as the name of the file in the simulation and on the host. When there are two arguments, the first is the filename in the simulation, and the second is the name on the host. Change-Id: I402925a9ff89665bee9910fb18b7f8b06b8f7d35 Reviewed-on: https://gem5-review.googlesource.com/4850 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Gabe Black <gabeblack@google.com>
2017-09-26sim: Give the NullSimObject singleton a _name.Gabe Black
The name is 'Null', and is what __str__ returns. Change-Id: I113f52496f5e9133b8d03206289b719fda003582 Reviewed-on: https://gem5-review.googlesource.com/4845 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Gabe Black <gabeblack@google.com>
2017-09-26sim: Add a NullSimObject.descendants function.Gabe Black
Null simobjects don't have any descendants. Change-Id: Ia43a99056709f422c9c817c017912d23d689fb1e Reviewed-on: https://gem5-review.googlesource.com/4844 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Gabe Black <gabeblack@google.com>
2017-09-26sim: Add a clear_parent function to NullSimObject.Gabe Black
Change-Id: I3842176f147997105fcc62aaf9cb93b9896708be Reviewed-on: https://gem5-review.googlesource.com/4843 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Gabe Black <gabeblack@google.com>
2017-09-26sim: Check the SimObjectVector.has_parent function to use the "any" function.Gabe Black
The existing code was essentially doing the same thing, but in a more roundabout and obscure way. One difference between the two versions is that I believe this will stop as soon as it encounters an element without a parent, where the original version would call has_parent() on all the elements regardless. Change-Id: Ia1fef3083fc88fca11f8ecfca453476e33194695 Reviewed-on: https://gem5-review.googlesource.com/4842 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Gabe Black <gabeblack@google.com>
2017-09-26sim: Only consider non-NULL elements in SimObjectVector.has_parent.Gabe Black
NullSimObject doesn't have a has_parent function, and it's not clear what its return value should be if one were added. The appropriate value seems to depend on why some other bit of code is checking if there's a parent in the first place. In SimObjectVector, the has_parent function is checking whether all of its elements have a parent. In this particular case, the most reasonable thing to do seems to be to just skip those elements. Change-Id: I5f8cad66d1b22c5e37962492fd77cff9371e5af8 Reviewed-on: https://gem5-review.googlesource.com/4841 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Gabe Black <gabeblack@google.com>
2017-09-26sim: Add a set_parent to NullSimObject which does nothing.Gabe Black
This lets attempts to set_parent on NullSimObject fall away harmlessly without having to add a bunch of checks whenever set_parent is called. Change-Id: I6d3510772ba71e765c4739e486e9f3d2460c4e11 Reviewed-on: https://gem5-review.googlesource.com/4840 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Gabe Black <gabeblack@google.com>
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