gem5 - gem5

Age	Commit message (Collapse)	Author
2011-03-01	Ruby: Mention that Ruby's bound checking option only applies to Ruby.	Gabe Black

2011-02-27	X86: If PCI config space is disabled, pass through to regular IO addresses.	Gabe Black

2011-02-27	X86: Update X86_FS stats.	Gabe Black

2011-02-27	X86: Use regular read requests in the walker instead of read exclusive.	Gabe Black

2011-02-27	inorder: bzip2 regression update	Korey Sewell

2011-02-26	getopt: Remove GPL code.	Nathan Binkert
	This code is unused and should never have been committed
2011-02-25	Ruby: Remove store buffer	Nilay Vaish
	This patch removes the store buffer from Ruby. It is not in use currently. Since libruby is being and store buffer makes calls to libruby, it is not possible to maintain it until substantial changes are made.
2011-02-25	Ruby: Remove libruby	Nilay Vaish
	This patch removes libruby_internal.hh, libruby.hh and libruby.cc. It moves the contents to libruby.hh to RubyRequest.hh and RubyRequest.cc files.
2011-02-25	Ruby: Make Address.hh independent of RubySystem	Nilay Vaish
	This patch changes Address.hh so that it is not dependent on RubySystem. This dependence seems unecessary. All those functions that depend on RubySystem have been moved to Address.cc file.
2011-02-25	Ruby: Make DataBlock.hh independent of RubySystem	Nilay Vaish
	This patch changes DataBlock.hh so that it is not dependent on RubySystem. This dependence seems unecessary. All those functions that depende on RubySystem have been moved to DataBlock.cc file.
2011-02-25	O3CPU: Fix iqCount and lsqCount SMT fetch policies.	Timothy M. Jones
	Fixes two of the SMT fetch policies in O3CPU that were returning the count of instructions in the IQ or LSQ rather than the thread ID to fetch from.
2011-02-24	Configs: Explicitly import env in Benchmarks.py	Gabe Black
	env was being implicitly imported into Benchmarks.py through SysPaths.py. This change brings it in explicitly in the file where it's used.
2011-02-23	regress: MOESI_hammer memtest updates	Brad Beckmann

2011-02-23	ruby: automate permission setting	Brad Beckmann
	This patch integrates permissions with cache and memory states, and then automates the setting of permissions within the generated code. No longer does one need to manually set the permissions within the setState funciton. This patch will faciliate easier functional access support by always correctly setting permissions for both cache and memory states. --HG-- rename : src/mem/slicc/ast/EnumDeclAST.py => src/mem/slicc/ast/StateDeclAST.py rename : src/mem/slicc/ast/TypeFieldEnumAST.py => src/mem/slicc/ast/TypeFieldStateAST.py
2011-02-23	MOESI_hammer: cache probe address clean up	Brad Beckmann

2011-02-23	ruby: cleaned up access permission enum	Brad Beckmann

2011-02-23	ruby: removed unsupported protocol files	Brad Beckmann

2011-02-23	inorder: add 00.gzip and 60.bzip2 regression tests	Korey Sewell

2011-02-23	inorder: InstSeqNum bug	Korey Sewell
	Because int and not InstSeqNum was used in a couple of places, you can overflow the int type and thus get wierd bugs when the sequence number is negative (or some wierd value)
2011-02-23	inorder: dyn inst initialization	Korey Sewell
	remove constructors that werent being used (it just gets confusing) use initialization list for all the variables instead of relying on initVars() function
2011-02-23	inorder: cache packet handling	Korey Sewell
	-use a pointer to CacheReqPacket instead of PacketPtr so correct destructors get called on packet deletion - make sure to delete the packet if the cache blocks the sendTiming request or for some reason we dont use the packet - dont overwrite memory requests since in the worst case an instruction will be replaying a request so no need to keep allocating a new request - we dont use retryPkt so delete it - fetch code was split out already, so just assert that this is a memory reference inst. and that the staticInst is available
2011-02-23	ARM: Update regression tests for preceeding changes.	Ali Saidi

2011-02-23	Mem: Print out memory when access > 8 bytes	Ali Saidi

2011-02-23	ARM: Set ITSTATE correctly after FlushPipe	Ali Saidi

2011-02-23	ARM: This panic can be hit during misspeculation so it can't exist.	Ali Saidi

2011-02-23	ARM: Bad interworking warn way to noisy when running real code w/misspeculation.	Ali Saidi

2011-02-23	O3: When a prefetch causes a fault, don't record it in the inst	Ali Saidi

2011-02-23	ARM: NEON instruction templates modified to set the predicate flag to false ↵	Giacomo Gabrielli
	when needed.
2011-02-23	O3: If there is an outstanding table walk don't let the inst queue sleep.	Ali Saidi
	If there is an outstanding table walk and no other activity in the CPU it can go to sleep and never wake up. This change makes the instruction queue always active if the CPU is waiting for a store to translate. If Gabe changes the way this code works then the below should be removed as indicated by the todo.
2011-02-23	ARM: Squash state on FPSCR stride or len write.	Ali Saidi

2011-02-23	ARM: Mark store conditionals as such.	Matt Horsnell

2011-02-23	ARM: Do something for ISB, DSB, DMB	Ali Saidi

2011-02-23	ARM: Fix bug that let two table walks occur in parallel.	Ali Saidi

2011-02-23	Includes: Don't include isa_traits.hh and use the TheISA namespace unless ↵	Ali Saidi
	really needed.
2011-02-23	ARM: Make Noop actually decode to a noop and set it's instflags.	Ali Saidi

2011-02-23	O3: Fix bug when a squash occurs right before TLB miss returns.	Ali Saidi
	In this case we need to throw away the TLB miss, not assume it was the one we were waiting for.
2011-02-23	ARM: Delete OABI syscall handling.	Ali Saidi
	We only support EABI binaries, so there is no reason to support OABI syscalls. The loader detects OABI calls and fatal() so there is no reason to even check here.
2011-02-23	CLCD: Fix some serialization bugs with the clcd controller.	Ali Saidi

2011-02-23	ARM: Clarifies creation of Linux and baremetal ARM systems.	Ali Saidi
	makeArmSystem creates both bare-metal and Linux systems more cleanly. machine_type was never optional though listed as an optional argument; a system such as "RealView_PBX" must now be explicitly specified. Now that it is a required argument, the placement of the arguments has changed slightly requiring some changes to calls that create ARM systems.
2011-02-23	ARM: Add support for read of 100MHz clock in system controller.	Ali Saidi

2011-02-23	ARM: Reset simulation statistics when pref counters are reset.	Ali Saidi
	The ARM performance counters are not currently supported by the model. This patch interprets a 'reset performance counters' command to mean 'reset the simulator statistics' instead.
2011-02-23	ARM: Adds dummy support for a L2 latency miscreg.	Ali Saidi

2011-02-23	configs: cache: add cache line size option	Korey Sewell

2011-02-23	configs: set default cache params	Korey Sewell
	It's confusing (especially to new users), when you are setting some standard parameters (as defined in Options.py) and they aren't reflected in the simulations so we might as well link the settings in CacheConfig.py to those in Options.py
2011-02-23	ruby: extend dprintfs for RubyGenerated TraceFlag	Korey Sewell
	"executing" isnt a very descriptive debug message and in going through the output you get multiple messages that say "executing" but nothing to help you parse through the code/execution. So instead, at least print out the name of the action that is taking place in these functions.
2011-02-23	ruby: cleaning up RubyQueue and RubyNetwork dprintfs	Korey Sewell
	Overall, continue to progress Ruby debug messages to more of the normal M5 debug message style - add a name() to the Ruby Throttle & PerfectSwitch objects so that the debug output isn't littered w/"global:" everywhere. - clean up messages that print over multiple lines when possible - clean up duplicate prints in the message buffer
2011-02-22	m5: merged in hammer fix	Brad Beckmann

2011-02-19	Ruby: Machine Type missing in MOESI CMP directory protocol	Nilay Vaish
	In certain actions of the L1 cache controller, while creating an outgoing message, the machine type was not being set. This results in a segmentation fault when trace is collected. Joseph Pusudesris provided his patch for fixing this issue.
2011-02-19	Ruby: clean MOESI CMP directory protocol	Nilay Vaish
	The L1 cache controller file contains references to foo and goo queues, which are not in use at all. These have been removed.
2011-02-18	m5: merge inorder/release-notes/make_release changes	Korey Sewell