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2010-01-12since totalInstructions() is impl'ed by all the cpus, make it an abstract ↵Lisa Hsu
base class.
2010-01-12faults: i think these fault invocations should be panic and not fatal. it ↵Lisa Hsu
definitely made implementing a trace cpu easier this way.
2010-01-02MIPS: Update the stats of the RUBY version of the regressions.Gabe Black
2009-12-31MIPS: Update stats for updated initial environment.Gabe Black
2009-12-31MIPS: Beef up process initialization.Matt DeVuyst
2009-12-31MIPS: Implement the SE mode version of rdhwr.Gabe Black
2009-12-31MIPS: Fix decoding of the rdhwr instruction.Gabe Black
2009-12-31MIPS: Implement the set_thread_area system call.Gabe Black
2009-12-31MIPS: Create an artificial control register to hold the thread pointer.Gabe Black
In Linux, the set_thread_area system call stores the address of the thread local storage area into a field of the current thread_info structure. Later, to access that value, the program uses the rdhwr instruction to read a "hardware register" with index 29. The 64 bit MIPS manual, volume II, says that index 29 is reserved for a future ABI extension and should cause a "Reserved Instruction Exception". In Linux (and potentially other ISAs) that exception is trapped and emulated to return the value stored by set_thread_area as if that were actually stored by a physical register. The tp_value address (as named in the Linux kernel) is ironically stored as a control register so that it goes with a particular ThreadContext. Syscall emulation will use that to emulate storing to the OS's thread info structure, and rdhwr will emulate faulting and returning that value from software by returning the value itself, as if it was in hardware. In other words, we fake faking the register in SE mode. In an FS mode implementation it should work as specified in the manual.
2009-12-31MIPS: Extract CPU pointer from the thread context in scheduleCP0 setMiscReg.Gabe Black
The MIPS ISA object expects to be constructed with a CPU pointer it uses to look at other thread contexts and allow them to be manipulated with control registers. Unfortunately, that differs from all the other ISA classes and would complicate their implementation. This change makes the event constructor use a CPU pointer pulled out of the thread context passed to setMiscReg instead.
2009-12-21MIPS: Add missing syscall slots.Gabe Black
These are all after the existing ones, suggesting they were added after the original list was created.
2009-12-20Alpha: Implement MVI and remaining BWX instructions.Soumyaroop Roy
2009-12-19X86: Add a latency that describes how long an interrupt takes to propagate ↵Gabe Black
through the IO APIC.
2009-12-19X86: Record the memory mode when building an X86 system.Gabe Black
2009-12-19X86: Add a common named flag for signed media operations.Gabe Black
2009-12-19X86: Create a common flag with a name to indicate high multiplies.Gabe Black
2009-12-19X86: Create a common flag with a name to indicate scalar media instructions.Gabe Black
2009-11-18m5: refreshed the ruby memtest regression statsBrad Beckmann
2009-11-18Resurrection of the CMP token protocol to GEM5Brad Beckmann
2009-11-18m5: improvements to the ruby_fs.py fileBrad Beckmann
2009-11-18ruby: removed the chip pointer from MessageBufferBrad Beckmann
The Chip object no longer exists and thus is removed from the MessageBuffer constructor.
2009-11-18ruby: added error message to isinstance checkBrad Beckmann
Added error message when a symbol is not an instance of a particular expected type.
2009-11-18ruby: Added boolean to State Machine parametersBrad Beckmann
* * * ruby: Removed primitive .hh includes
2009-11-18m5: Added the default m5out directory to the hg ignore listBrad Beckmann
2009-11-18ruby: The persistent table files from GEMSBrad Beckmann
These files are need by the MOESI_CMP_token protocol.
2009-11-18ruby: MOESI hammer support for DMA reads and writesBrad Beckmann
2009-11-18ruby: Added a memory controller feature to MOESI hammerBrad Beckmann
2009-11-18ruby: Hammer ruby configuration supportBrad Beckmann
2009-11-18ruby: Changes necessary to get the hammer protocol to work in GEM5Brad Beckmann
2009-11-18ruby: added the original hammer protocols from old rubyBrad Beckmann
2009-11-18ruby: returns the number of LLC needed for broadcastBrad Beckmann
Added feature to CacheMemory to return the number of last level caches. This count is need for broadcast protocols such as MOESI_hammer.
2009-11-18ruby: cache configuration fix to use bytesBrad Beckmann
Changed cache size to be in bytes instead of kb so that testers can use very small caches and increase the chance of writeback races.
2009-11-18ruby: fix CacheMemory destructorBrad Beckmann
2009-11-18ruby: split CacheMemory.hh into a .hh and a .ccBrad Beckmann
2009-11-18ruby: Added default names to message buffersBrad Beckmann
Added default names to message buffers created by the simple network.
2009-11-18ruby: slicc method error fixBrad Beckmann
Added error message when a method call is not supported by an object.
2009-11-18ruby: slicc action error fixBrad Beckmann
Small fix to the State Machine error message when duplicate actions are defined.
2009-11-18ruby: slicc state machine error fixesBrad Beckmann
Added error messages when: - a state does not exist in a machine's list of known states. - an event does not exist in a machine - the actions of a certain machine have not been declared
2009-11-18ruby: Removed unused action z_stallBrad Beckmann
2009-11-18m5: Added option to take a checkpoint at the end of simulationBrad Beckmann
2009-11-18m5: Fixed bug in atomic cpu destructorBrad Beckmann
2009-11-18ruby: fixed dma mi example to work with multiple dma portsBrad Beckmann
2009-11-18m5: removed master and slave deletions.Brad Beckmann
The unresolved destructor call caused a seg fault when called.
2009-11-18m5: fixed destructor to deschedule the tickEvent and eventBrad Beckmann
2009-11-18ruby: getPort function fixBrad Beckmann
Fixed RubyMemory::getPort function to not pass in a -1 for the idx parameter
2009-11-18ruby: Fixed Directory memory destructorBrad Beckmann
2009-11-18m5: Moved profile option since Simulation depends on it.Brad Beckmann
2009-11-18m5: Added isValidSrc and isValidDest calls to packet.hhBrad Beckmann
2009-11-18ruby: included ruby config parameter ports per coreBrad Beckmann
Slightly improved the major hack need to correctly assign the number of ports per core. CPUs have two ports: icache + dcache. MemTester has one port.
2009-11-18ruby: Added error check for openning the ruby config fileBrad Beckmann