summaryrefslogtreecommitdiff
AgeCommit message (Expand)Author
2006-08-25Update for new regression test structure.Steve Reinhardt
2006-08-24Update a few bogus reference outputsSteve Reinhardt
2006-08-22Still need LL/SC support in cache, add hack to always return success for nowRon Dreslinski
2006-08-22Commiting a version of the multi-phase snoop atomic bus so people can see the...Ron Dreslinski
2006-08-22Merge zizzer:/z/m5/Bitkeeper/newmemRon Dreslinski
2006-08-22Update refs for tru64 with initialized cache statsRon Dreslinski
2006-08-21Fix annulled unconditional branchesGabe Black
2006-08-21Merge zizzer.eecs.umich.edu:/bk/newmemGabe Black
2006-08-21SConstruct:Steve Reinhardt
2006-08-21Merge zizzer.eecs.umich.edu:/bk/newmemGabe Black
2006-08-21Update REFs for statistics patch in cacheRon Dreslinski
2006-08-21Got rid of the aux_data array since it shouldn't have existed.Gabe Black
2006-08-21Fixed the parameters to memset. sizeof(regSegments[x]) may have been returnin...Gabe Black
2006-08-21Two bugs found by my tracing tool.Gabe Black
2006-08-21Merge zizzer:/z/m5/Bitkeeper/newmemRon Dreslinski
2006-08-21Changes so that time in the packet is actually set properly.Ron Dreslinski
2006-08-21fs.py:Steve Reinhardt
2006-08-20TEST_CPU_MODELS isn't used anymore.Steve Reinhardt
2006-08-20Add Alpha Linux version of "hello world" test.Steve Reinhardt
2006-08-20Alpha "hello world" test is really Tru64 not Linux... oops.Steve Reinhardt
2006-08-20configs/example/fs.py:Steve Reinhardt
2006-08-19SConscript:Steve Reinhardt
2006-08-18Update reference outputsSteve Reinhardt
2006-08-18Add caches in, fix cpu.mem paramSteve Reinhardt
2006-08-17Changes to build m5.fastSteve Reinhardt
2006-08-17Add readfile back in.Kevin Lim
2006-08-17Merge zizzer:/bk/newmemAli Saidi
2006-08-17add default range to PhysicalMemoryAli Saidi
2006-08-17SConstruct:Steve Reinhardt
2006-08-17AUTHORS:Lisa Hsu
2006-08-17Merge zizzer:/bk/newmemLisa Hsu
2006-08-17make tree rcS files reflect what we've been actually using in /dist.Lisa Hsu
2006-08-16we don't want the old memory timing dram model eitherAli Saidi
2006-08-16Fix the caches not working in the regressionRon Dreslinski
2006-08-16Merge zizzer:/bk/newmemAli Saidi
2006-08-16DRAM Memory doesn't crash the simulator now.. still untested.Ali Saidi
2006-08-16we don't want the splash2 config files either, they haven't been converted yetAli Saidi
2006-08-16Add checkpointing and configuration stuff to the people that worked on itNathan Binkert
2006-08-16Added in SPARC ISA specifically. Thanks to whoever fleshed out my entry.Gabe Black
2006-08-16add etherdump file optionAli Saidi
2006-08-16Merge zizzer:/bk/newmemAli Saidi
2006-08-16Fix Physical Memory to allow memory sizes bigger than 128MB.Ali Saidi
2006-08-16Merge zizzer.eecs.umich.edu:/z/m5/Bitkeeper/newmemSteve Reinhardt
2006-08-16More regression updates.Steve Reinhardt
2006-08-16Add in checkpointing in the frontend, so that when a checkpoint is called, th...Lisa Hsu
2006-08-16Minor regression fixes.Steve Reinhardt
2006-08-16AUTHORS:Korey Sewell
2006-08-16Tweak my author listRon Dreslinski
2006-08-16Merge zizzer:/z/m5/Bitkeeper/newmemRon Dreslinski
2006-08-16Fixes for Kevins O3 model to work with the blocking caches.Ron Dreslinski