Age | Commit message (Collapse) | Author |
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Update the system dir for the addition of parallel and dirty netperf
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re-do fixed dma latency
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delay is more or less folded into the packet time, but an additional
delay is possible representing crossing a long haul link, or some
switches, etc.
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the header, and fix so that it doesn't keep requesting the payload bus
if the sendRequest was unsuccesful.
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and to free up the header bus by returning false. If there is no
header splitting it will work normally.
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of stats
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The two busses are labeled header/payload. The header_size
designates the number of cache blocks to send on the header bus.
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take time
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we switch over to making ticks represent time directly.
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to memory in different configurations
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into ziff.eecs.umich.edu:/z/binkertn/research/m5/latest
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cpu/base_cpu.cc:
#ifdef FULL_SYSTEM
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arch/alpha/isa_desc:
Just to make sure, remove the new copy instructions until everything works.
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data DMAs from touching the memory system. They can
still have a latency though if configured.
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cpu/base_cpu.cc:
gah! copy the interrupt status on switchover
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into zizzer.eecs.umich.edu:/.automount/ziff/z/binkertn/research/m5/latest
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code.
base/statistics.hh:
We're getting rid of FS_MEASURE, but for now, we're going
to still use a compile time flag to turn on and off binning
of statistics. (The flag is STATS_BINNING)
cpu/exec_context.cc:
cpu/exec_context.hh:
kern/tru64/tru64_system.cc:
get rid of FS_MEASURE
cpu/simple_cpu/simple_cpu.cc:
yank the function call tracking code out of the cpu and move
it into the software context class itself.
kern/tru64/tru64_system.hh:
get rid of FS_MEASURE
move all of the tacking stuff to the same place.
sim/system.hh:
cleanup
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into ziff.eecs.umich.edu:/z/binkertn/research/m5/latest
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base/trace.cc:
code to set/clear/print trace flags from the debugger.
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vary in size, so we're explicit about the fields.
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dev/alpha_console.cc:
setAddrRange -> addAddrRange
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arch/alpha/ev5.cc:
actually implement the cycle count register
arch/alpha/isa_desc:
the rpcc instruction really just reads the cycle count
register
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arch/alpha/ev5.cc:
Handle writing IPR_CC and IPR_CC_CTL slightly more intelligently.
(Very slightly).
arch/alpha/isa_desc:
Upper half of rpcc result comes from value written
to IPR_CC, not actual cycle counter.
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arch/alpha/isa_desc:
Add copy_load and copy_store insts (ldf and stf respectively)
cpu/simple_cpu/simple_cpu.hh:
Add copy functions to SimpleCPU as well
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arch/alpha/osfpal.cc:
Add a string for copypal.
arch/alpha/osfpal.hh:
Add a code for copypal.
cpu/static_inst.hh:
Add an IsCopy flag.
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the request locally until it is retransmitted.
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it actually do something on FullCPU. Still disabled, as it
causes detailed-boot to hang when you turn it on.
arch/alpha/isa_desc:
Add EAComp and MemAcc pseudo-instructions to prefetch StaticInst.
cpu/simple_cpu/simple_cpu.hh:
Changed prefetch() return type from Fault to void.
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won't accidentally be issued to the memory system.
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