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2018-10-16systemc: Print an Info when setting a tracefile's time unit.Gabe Black
This matches Accellera's output for the tests. Change-Id: Ie67fd673a980b8ca2fdcd8f357ff7993a9091221 Reviewed-on: https://gem5-review.googlesource.com/c/12972 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com>
2018-10-16systemc: Move some constants out of sc_time.cc for other files to use.Gabe Black
Change-Id: Ic88c6834dfe980022e58a3d859ea53193a55bbb1 Reviewed-on: https://gem5-review.googlesource.com/c/12971 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com>
2018-10-16systemc: Add a warning to sc_interface::default_event.Gabe Black
The default implementation returns a dummy event, but in the Accellera implementation it also prints a warning. Print a warning as well, so that the output matches for the tests. Change-Id: I1ae2755685515c3fe538f4075af396e963cf155d Reviewed-on: https://gem5-review.googlesource.com/c/12970 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com>
2018-10-16systemc: Filter out an Info about delta cycles and pseudo timesteps.Gabe Black
In the Accellera implementation, every time a delta cycle is traced a check is done to see if the user has been told what the pseudo timestep is. To avoid doing that check over and over, we'll leave that out and tell the verify.py to ignore that message in the reference output. Change-Id: I825f05394dccf03e951d29561a11c3cc6d4bcda7 Reviewed-on: https://gem5-review.googlesource.com/c/12969 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com>
2018-10-16systemc: Check the process type when using sc_join.Gabe Black
Method processes aren't allowed in an sc_join. Change-Id: I5c8421a396dbe261645a074df514f69fc652c9c8 Reviewed-on: https://gem5-review.googlesource.com/c/12968 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com>
2018-10-16systemc: Make sure the right type process is running when calling wait.Gabe Black
That function is only allowed when running a thread or cthread. Change-Id: Idf98b70018169d4f724aa8168f3c4e8161f0b83d Reviewed-on: https://gem5-review.googlesource.com/c/12967 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com>
2018-10-16systemc: Add an error check to sc_time.Gabe Black
Change-Id: Ie525a1624a6496a51277fb984cbfeec21eb79749 Reviewed-on: https://gem5-review.googlesource.com/c/12966 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com>
2018-10-16systemc: Add some error checks to sc_export.Gabe Black
Change-Id: Ib0c14a5c7dad37b33d61c9b406f6b84121d94e46 Reviewed-on: https://gem5-review.googlesource.com/c/12965 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com>
2018-10-16systemc: Implement general and VCD trace support.Gabe Black
This doesn't include WIF trace support, but does make allowances for adding it in the future. Change-Id: Ifb62f40a7d8a13e94463930a44ac4b1cf41e3009 Reviewed-on: https://gem5-review.googlesource.com/c/12826 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com>
2018-10-16systemc: Don't schedule the ready event unnecessarily.Gabe Black
If we're already going to process the thing we'd be scheduling it to process, just let the existing invocation get to it. Change-Id: Ifeebc80903065567fc0eed02beefec6156b22ff7 Reviewed-on: https://gem5-review.googlesource.com/c/12964 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com>
2018-10-16systemc: Fix the implementation of sc_event::triggered.Gabe Black
This function just returned false. The new implementation uses the scheduler's changeStamp function to keep track of how recently the event was triggered so it can return return the right value. Change-Id: Idf61cd459e53e224a33d3e53c16210f5e0a99a3a Reviewed-on: https://gem5-review.googlesource.com/c/12825 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com>
2018-10-16systemc: Teach verify.py how to verify vcd files.Gabe Black
The reference output skips the first 7 lines which have volatile info like the current time. Change-Id: I9c173ff3903982a07349ca6957ab25e07bdf8e54 Reviewed-on: https://gem5-review.googlesource.com/c/12824 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com>
2018-10-16systemc: Fix the default width values for the various sc_trace-s.Gabe Black
These were all set to 8 * sizeof(char) instead of using the size of the actual data type being traced. Also add a very simple implementation to the generic sc_signal_in_if<T> sc_trace which just delegates to the sc_trace of the underlying type T. Change-Id: I129df46ef9d49705dc3dac76e30c0a3652c981eb Reviewed-on: https://gem5-review.googlesource.com/c/12818 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com>
2018-10-16systemc: Fix a typo in verify.py.Gabe Black
In the generic (non-console output) output checker, a variable should have been called self.test, but was called self.text. Change-Id: I2518d6ff01c51fc195eef2b61e987d1b3104c89b Reviewed-on: https://gem5-review.googlesource.com/c/12817 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com>
2018-10-16systemc: Add an error check whether an interface is alread bound to a port.Gabe Black
Change-Id: I06e3484176c0c06daa28f7be0ed8437b3b15ddb2 Reviewed-on: https://gem5-review.googlesource.com/c/12816 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com>
2018-10-16systemc: Add some additional error checks.Gabe Black
Change-Id: I19c5e6f1795c2777dbe7d210cfa01f6ced2020f3 Reviewed-on: https://gem5-review.googlesource.com/c/12815 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com>
2018-10-16systemc: Change an error message to match the reference outputs.Gabe Black
This is different from the message the Accellera implementation would print, so it looks like it wouldn't pass this test as is. Change-Id: I0286fd3e3df7bc3e87f38c35086a32d8dec0bcc9 Reviewed-on: https://gem5-review.googlesource.com/c/12814 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com>
2018-10-13mem-cache: Add missing includes in TreePLRUDaniel
Add missing includes to TreePLRU files. Change-Id: Ia1e7b2aa91eec8a30b6dccf513cca37a3058b350 Reviewed-on: https://gem5-review.googlesource.com/c/13477 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2018-10-13mem: Get rid of some stray lines which ended up in packet.hh.Gabe Black
These were left in by mistake when refactoring patches for review. Change-Id: I4c39b5a3e2a2d3957e725a6ffcf48c25b8a69f2e Reviewed-on: https://gem5-review.googlesource.com/c/13495 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com>
2018-10-12arch: Explicitly specify the endianness in the generic mem helpers.Gabe Black
This avoids using the accessors which automatically assume an endianness, requiring the memory system to know what the guest ISA is. Change-Id: I863fa4116f00e77b801a2f8ea2fbe34e7f55fd5f Reviewed-on: https://gem5-review.googlesource.com/c/13461 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-10-12mips: Use little endian packet accessors.Gabe Black
We know data is little endian, so we can use those accessors explicitly. Change-Id: I6220a543686b1d45d26973391b028dc04ce85dd2 Reviewed-on: https://gem5-review.googlesource.com/c/13460 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Gabe Black <gabeblack@google.com>
2018-10-12alpha: Use little endian packet accessors.Gabe Black
We know data is little endian, so we can use those accessors explicitly. Change-Id: Ieb9c1eb8a4fec31ee69cbbfd8c1afdf9f64de366 Reviewed-on: https://gem5-review.googlesource.com/c/13459 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Gabe Black <gabeblack@google.com>
2018-10-12sparc: Use big endian packet accessors.Gabe Black
We know data is big endian, so we can use those accessors explicitly. Change-Id: I06fe35254433b20db05f5f10d0ca29a44d47c301 Reviewed-on: https://gem5-review.googlesource.com/c/13458 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Gabe Black <gabeblack@google.com>
2018-10-12arm: Use little endian packet accessors.Gabe Black
We know data is little endian, so we can use those accessors explicitly. Change-Id: Iee337109fcda134e1ac5a700e5141fd7060f9c45 Reviewed-on: https://gem5-review.googlesource.com/c/13457 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-10-12x86: Use little endian packet accessors.Gabe Black
We know data is little endian, so we can use those accessors explicitly. Change-Id: I09aa7f1e525ad1346e932ce4a772b64bf59dc350 Reviewed-on: https://gem5-review.googlesource.com/c/13456 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Gabe Black <gabeblack@google.com>
2018-10-12mem: Expose the raw packet accessor functions.Gabe Black
This avoids a place where data has its endianness switched so that when the endianness based accessors switch it back it returns to normal. It also makes it easier to show intent when accessing single bytes where endianness doesn't matter, and there's no contextual endianness. Change-Id: I1b97396c1b9bb39727d35112d90e3969e5fe0aab Reviewed-on: https://gem5-review.googlesource.com/c/13455 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2018-10-12dev: Include the platform base class even in NULL_ISA builds.Gabe Black
These classes don't have any ISA specific aspects. Change-Id: Ifefb12d23e4aee8e3fd56f0a1eb3d9ad00e733a0 Reviewed-on: https://gem5-review.googlesource.com/c/13467 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-10-12syscall_emul: update arm uname release to 3.7.0+Ciro Santilli
Trying to compile an ARM C hello world with arm-linux-gnueabihf-gcc from Ubuntu 16.04 leads to a runtime failure with se.py: FATAL: kernel too old because the glibc tests if the kernel is at least 3.2.0, and gem5 was reporting 3.0.0. Furthermore, it is hard to obtain such toolchain at all: for example crosstool-NG currently only allows for minimum kernels above 3.2.0. 3.7.0+ was chosen to match the aarch64 value, as it is likely that the level of support will be very similar. This commit does not guarantee that full 3.7.0 is supported, but it is not likely that we had full 3.0.0 support previously either. However, it is more likely that such support will be eventually achieved if users can at least try out their programs and implement the missing system calls as they are found. Change-Id: I8df3763ae49788a6cb11cb0920e8202cd56b0f09 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/12986 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-10-11mem-cache: Factor ReplaceableEntry outDaniel R. Carvalho
ReplaceableEntry is referenced by many classes that do not necessarily need access to the replacement policies. Therefore, in order to allow better compilation units, we factor it out to a new file. Change-Id: I0823567bf1ca336ffcdf783682ef473e8878d7fd Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br> Reviewed-on: https://gem5-review.googlesource.com/c/13418 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2018-10-11mem-cache: Move sector_blks to tags folderDaniel R. Carvalho
Move sector_blks.hh and sector_blks.cc to the tags folder, as its usage scope is restricted to the tags, and caches should not be aware of them. Change-Id: Ia7a71f51ec251d827872daf108c87da543a0ba57 Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br> Reviewed-on: https://gem5-review.googlesource.com/c/13417 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2018-10-11mem-cache: Rename blk.cc/hh to cache_blk.cc/hhDaniel R. Carvalho
Rename the files blk.cc and blk.hh to cache_blk.cc and cache_blk.hh to comply with the usual file-class naming rules. Change-Id: I8af45df3e4b8dd934fd9929ec914fb230cb2cb09 Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br> Reviewed-on: https://gem5-review.googlesource.com/c/13416 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2018-10-11mem-cache: Virtualize block printDaniel R. Carvalho
Encapsulate and virtualize block print, so that relevant information can be easily printed anywhere. Change-Id: I91109c29c126755183a0fd2b4446f5335e64076b Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br> Reviewed-on: https://gem5-review.googlesource.com/c/13415 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2018-10-10mem-cache: Create Tree-PLRU replacement policyDaniel R. Carvalho
Implementation of a Tree-PLRU replacement policy. It is based on the assumption that a set associative cache is used. Change-Id: I74b227e88fd6c93aab5bb2cd0e8730376db28f52 Reviewed-on: https://gem5-review.googlesource.com/c/11106 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2018-10-10mem-cache: Remove CacheSet.hhDaniel R. Carvalho
Replacement policies aren't aware of cache sets and do not organize blocks based on replacement data. Block search is independent of block placement. Besides, indexing policies have their own way of addressing the sets, therefore there is no need to use this class anymore. BlkType has been removed, as it wasn't being used. Change-Id: Ia79c2a491e59f295c8d60a0466c317eb0e2bdab9 Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br> Reviewed-on: https://gem5-review.googlesource.com/c/9782 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2018-10-10mem-cache: Split Tags for indexing policiesDaniel R. Carvalho
Split indexing functionality from tags, so that code duplication is reduced when adding new classes that use different indexing policies, such as set associative, skewed associative or other hash-based policies. An indexing policy defines the mapping between an address' set and its physical location. For example, a conventional set assoc cache maps an address to all ways in a set using an immutable function, that is, a set x is always mapped to set x. However, skewed assoc caches map an address to a different set for each way, using a skewing function. FALRU has been left unmodified as it is a specialization with its own complexity. Change-Id: I0838b41663f21eba0aeab7aeb7839e3703ca3324 Reviewed-on: https://gem5-review.googlesource.com/c/8885 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2018-10-10mem-cache: Use set and way for ReplaceableEntryDaniel R. Carvalho
Replaceable entries belong to table-like structures, and therefore they should be indexable by combining a row and a column. These, using conventional cache nomenclature translate to sets and ways. Make these entries aware of their sets and ways. The idea is to make indexing policies usable by other table-like structures. In order to do so we move sets and ways to ReplaceableEntry, which will be the common base among table entries. Change-Id: If0e3dacf9ea2f523af9cface067469ccecf82648 Reviewed-on: https://gem5-review.googlesource.com/c/12764 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2018-10-10mem-cache: Use possible locations to find blockDaniel R. Carvalho
Use possible locations to find block to make it placement policy independent. Change-Id: I4c9d9e1e1ff91ce12e85ca1970f927d8f4f5a93b Reviewed-on: https://gem5-review.googlesource.com/c/8884 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2018-10-10mem-cache: Create tags initialization functionDaniel R. Carvalho
Having the blocks initialized in the constructor makes it harder to apply inheritance in the tags classes. This patch decouples the block initialization functionality from the constructor by using an init() function. It also sets the parent cache. Change-Id: I0da7fdaae492b1177c7cc3bda8639f79921fbbeb Reviewed-on: https://gem5-review.googlesource.com/c/11509 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2018-10-10mem-cache: Remove Packet dependency in TagsDaniel R. Carvalho
Decouple Tags from Packets, only extracting the necessary functionality for block insertion. As a side effect, create a new function to update common insertion statistics. Change-Id: I5c58f7c17de3255beee531f72a3fd25a30d74c90 Reviewed-on: https://gem5-review.googlesource.com/c/11098 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2018-10-09systemc: Implement the sc_signal_rv channel and ports.Gabe Black
Change-Id: Id1a3fd2ded224bbe94a4a65e0acf34a3547aedcc Reviewed-on: https://gem5-review.googlesource.com/c/12813 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com>
2018-10-09systemc: Ignore a gem5 warning about setting the stack size in verify.py.Gabe Black
This warning shouldn't make a test fail, but it's still useful to keep around. Change-Id: I9ebdbec804e11445edb82fa824ee0a6bce5943b0 Reviewed-on: https://gem5-review.googlesource.com/c/12812 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com>
2018-10-09systemc: Warn if sc_stop is called more than once.Gabe Black
Change-Id: Ief88b9af0119ba4b007f79905db2522b5f95b820 Reviewed-on: https://gem5-review.googlesource.com/c/12811 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com>
2018-10-09systemc: Check whether the simulation is running when creating sensitivities.Gabe Black
Change-Id: I499cde0d0eb45ba3287a8719174e1c794c1fb634 Reviewed-on: https://gem5-review.googlesource.com/c/12810 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com>
2018-10-09systemc: Handle nonstandard cthread sensitivities.Gabe Black
Accellera allows some non-standard values in the second position of the SC_CTHREAD macro. Do that as well, with the same special handling which automatically selects the positive edge of boolean ports/interfaces. Change-Id: I79594980898a17afc30fea6f77384589cbc3c250 Reviewed-on: https://gem5-review.googlesource.com/c/12809 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com>
2018-10-09systemc: Change how the scheduler orders processes.Gabe Black
The Accellera implementation looks like it does all the methods, then all the threads, and then loops back and tries again, and there are even comments in the code that suggests that. What it actually does, however, is runs all the methods, then runs a single thread if one is waiting, and then starts over. The effect is that the scheduler will run any methods first, then run threads until a method might have become ready, and then repeat. This will actually result in more mixing of threads and methods, more context switches, and worse performance, but it makes the regressions pass more. Change-Id: I7cb0485e26eed79204ff2a3c3ded27b973e0b7b0 Reviewed-on: https://gem5-review.googlesource.com/c/12808 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com>
2018-10-09systemc: Differentiate between notifying methods and threads.Gabe Black
The Accellera implementation notifies all types of method sensitivities first, and then notifies all the ones for threads. Change-Id: I5eda75958675ba518f008852148030e032f70d83 Reviewed-on: https://gem5-review.googlesource.com/c/12807 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com>
2018-10-09systemc: Rework how delayed sensitivities are handled.Gabe Black
Make BindInfo into a more general purpose Port class which mirrors sc_module and Module, sc_object and Object, etc. This tracks multiple bindings internally, and also pending sensitivities. Keep a global list of ports which are added in reverse order to match Accellera, and which is iterated over to finalize binding and for phase callbacks. This is as opposed to doing it one module at a time, and is to better match Accellera's ordering for the regressions. Also the sensitivity classes are now built with factory functions, which gets around problems calling virtual functions from their constructors or forgetting to having to have extra boilerplate each place they're constructed. The port class also now finalizes port or event finder sensitivities when its binding is completed, unless it's already complete in which case it does so immediately. Change-Id: I1b01689715c425b94e0f68cf0271f5c1565d8c61 Reviewed-on: https://gem5-review.googlesource.com/c/12806 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com>
2018-10-09systemc: Refactor sensitivities.Gabe Black
Dynamic and Static sensitivities used to be represented by the same classes, even though they're (almost) disjoint in how they worked. Also timeouts, which can be used alongside dynamic sensitivities, were handled by the sensitivities themselves. That meant that the sensitivity mechanism had to mix in more types of behaviors, increasing complexity. Also, the non-standard timed_out function Accellera includes is harder to implement if the path for timeouts and regular sensitivities are mixed together. This change splits up dynamic and static sensitivities and splits out timeouts. It also immitates the ordering Accellera uses when going through sensitivities for an event. Static sensitivities are triggered first in reverse order (why?), and then dynamic sensitivities are triggered in what amounts to reverse order. To delete a sensitivity which has been handled, it's swapped with the one in the last position, and then the vector is truncated to drop it at the end. This has the net effect of stirring the dynamic sensitivities, and isn't easily immitated using a different approach, even if other approaches would be more straightforward. Double check addSensitivity for event.hh Change-Id: I1e73dce386b95f68e9d6737deb8bed70ef717e0d Reviewed-on: https://gem5-review.googlesource.com/c/12805 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com>
2018-10-09systemc: Implement sc_buffer.Gabe Black
This required a small change to sc_signal so that the value change event and the change stamp for it were accessible. Change-Id: Ife0545d84f3b25e98da079786c30ffa51025cce7 Reviewed-on: https://gem5-review.googlesource.com/c/12804 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com>
2018-10-09systemc: Mark a few more tests as expected to return non-zero.Gabe Black
Change-Id: Ic23865d9c22909bb7482223548dbc7a46c356920 Reviewed-on: https://gem5-review.googlesource.com/c/12623 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com>
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