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AgeCommit message (Expand)Author
2012-04-14MEM: Separate snoops and normal memory requests/responsesAndreas Hansson
2012-04-14Regression: Add ANSI colours to highlight test statusAndreas Hansson
2012-04-14clang/gcc: Fix compilation issues with clang 3.0 and gcc 4.6Andreas Hansson
2012-04-13SCons: restore Werror option in src/SConscriptSteve Reinhardt
2012-04-12Stats: Update with use of std::map for ordered iteration in RubyAndreas Hansson
2012-04-12Ruby: Ensure order-dependent iteration uses an ordered mapAndreas Hansson
2012-04-09tests: Fix building unit tests.Gabe Black
2012-04-06rubytest: remove spurious printfBrad Beckmann
2012-04-06regress: ruby random tester and hammer stats updatesBrad Beckmann
2012-04-06ruby: set SimpleTiming as the default cpuBrad Beckmann
2012-04-06slicc: Controllers attached to Sequencers no longer have to be named L1Cache.Lisa Hsu
2012-04-06sim-ruby: checkpointing fixes and dependent eventq improvementsBrad Beckmann
2012-04-06slicc: fixed error message when the type has no inheritanceBrad Beckmann
2012-04-06MOESI_hammer: tbe allocation and dependent wakeup fixesBrad Beckmann
2012-04-06python: added __nonzero__ function to SimObject Bool paramsBrad Beckmann
2012-04-06MOESI_hammer: fixed bug with single cpu + flushes, then modified the regressi...Brad Beckmann
2012-04-06rubytest: seperated read and write ports.Brad Beckmann
2012-04-06MEM: Enable multiple distributed generalized memoriesAndreas Hansson
2012-04-05NetworkTest: remove unnecessary memory allocationTushar Krishna
2012-04-05Config: corrects the way Ruby attaches to the DMA portsNilay Vaish
2012-04-05Ruby: Fix the example configurations option parsingAndreas Hansson
2012-04-05Python: Make the All proxy traverse SimObject children as wellAndreas Hansson
2012-04-03Atomic: Remove the physmem_port and access memory directlyAndreas Hansson
2012-03-31X86: Fix address size handling so real mode works properly.Gabe Black
2012-03-30MEM: Remove legacy DRAM in preparation for memory updatesAndreas Hansson
2012-03-30Ruby: Remove the physMemPort and instead access memory directlyAndreas Hansson
2012-03-30MEM: Introduce the master/slave port sub-classes in C++William Wang
2012-03-30CPU: Unify initMemProxies across CPUs and simulation modesAndreas Hansson
2012-03-28Config: Change the way options are addedNilay Vaish
2012-03-27Config: Move setWorkCountOptions() to Simulation.pyNilay Vaish
2012-03-26range_map: Enable const find and iterationAndreas Hansson
2012-03-26Power: Change bitfield name to avoid conflicts with range_mapAndreas Hansson
2012-03-23Ruby: Fix Set::print for 32-bit hostsAndreas Hansson
2012-03-22MEM: Unify bus access methods and prepare for master/slave splitAndreas Hansson
2012-03-22MEM: Split SimpleTimingPort into PacketQueue and portsAndreas Hansson
2012-03-22Scons: Remove Werror=False in SConscript filesAndreas Hansson
2012-03-21Python: Fix a conditional expression that requires Python 2.5Andreas Hansson
2012-03-21ARM: Update stats for IT and conditional branch changesAli Saidi
2012-03-21ARM: Fix case where cond/uncond control is mis-specifiedNathanael Premillieu
2012-03-21ARM: Clean up condCodes in IT blocks.Ali Saidi
2012-03-21ARM: IT doesn't need to be serializing.Geoffrey Blake
2012-03-21O3: Fix sizing of decode to rename skid buffer.Andrew Lukefahr
2012-03-21ARM: Add RTC to PBX SystemKoan-Sin Tan
2012-03-21O3: Fix size of skid buffer between fetch and decode when widths are differentBrian Grayson
2012-03-21ARM: Fix uninitialized value in ARM RTC model.Ali Saidi
2012-03-19Garnet: Stats at vnet granularity + code cleanupTushar Krishna
2012-03-19gcc: Clean-up of non-C++0x compliant code, first stepsAndreas Hansson
2012-03-19clang: Fix recently introduced clang compilation errorsAndreas Hansson
2012-03-19scripts: Fix to ensure that port connection count is always setAndreas Hansson
2012-03-16ruby_fs.py: Add call to createInterruptController()Nilay Vaish
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