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2016-10-13mem: add DRAM powerdown timingOmar Naji
2016-10-13mem: make DDR4 x16Omar Naji
2016-10-13isa,arm: Add missing AArch32 FP instructionsMitch Hayenga
This commit adds missing non-predicated, scalar floating point instructions. Specifically VRINT* floating point integer rounding instructions and VSEL* floating point conditional selects. Change-Id: I23cbd1389f151389ac8beb28a7d18d5f93d000e7 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Nathanael Premillieu <nathanael.premillieu@arm.com>
2016-10-13ruby: Fix regressions and make Ruby configs Python packagesAndreas Hansson
This patch moves the addition of network options into the Ruby module to avoid the regressions all having to add it explicitly. Doing this exposes an issue in our current config system though, namely the fact that addtoPath is relative to the Python script being executed. Since both example and regression scripts use the Ruby module we would end up with two different (relative) paths being added. Instead we take a first step at turning the config modules into Python packages, simply by adding a __init__.py in the configs/ruby, configs/topologies and configs/network subdirectories. As a result, we can now add the top-level configs directory to the Python search path, and then use the package names in the various modules. The example scripts are also updated, and the messy path-deducing variations in the scripts are unified.
2016-10-07config: fix typo in cluster topology.Tushar Krishna
2016-10-07dev, arm: Make GenericTimer param handling more robustAndreas Sandberg
The generic timer needs a pointer to an ArmSystem to wire itself to the system register handler. This was previously specified as an instance of System that was later cast to ArmSystem. Make this more robust by specifying it as an ArmSystem in the Python interface and add a check to make sure that it is non-NULL. Change-Id: I989455e666f4ea324df28124edbbadfd094b0d02 Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
2016-10-06ruby: Add M5_VAR_USED before variables used only inside assert in garnet2.0.Tushar Krishna
This removes errors when building gem5.fast
2016-10-06ruby: garnet2.0Tushar Krishna
Revamped version of garnet with more optimized single-cycle routers, more configurability, and cleaner code.
2016-10-06ruby: remove the original garnet code.Tushar Krishna
Only garnet2.0 will be supported henceforth.
2016-10-06config: add port directions and per-router delay in topology.Tushar Krishna
This patch adds port direction names to the links during topology creation, which can be used for better printed names for the links or for users to code up their own adaptive routing algorithms. It also adds support for every router to have an independent latency value to support heterogeneous topologies with the subsequent garnet2.0 patch.
2016-10-06config: make internal links in network topology unidirectional.Tushar Krishna
This patch makes the internal links within the network topology unidirectional, thus allowing any deadlock-free routing algorithms to be specified from the topology itself using weights. This patch also renames Mesh.py and MeshDirCorners.py to Mesh_XY.py and MeshDirCorners_XY.py (Mesh with XY routing). It also adds a Mesh_westfirst.py and CrossbarGarnet.py topologies.
2016-10-06config: add a separate config file for the network.Tushar Krishna
This patch adds a new file configs/network/Network.py to setup the network, instead of doing that within Ruby.py.
2016-10-06ruby: rename networktest to garnet_synthetic_traffic.Tushar Krishna
networktest is essentially a collection of synthetic traffic patterns for the network. The protocol name and the tester having the same name led to multiple python configuration files with the same name, adding confusion. This patch renames networktest to garnet_synthetic_traffic, and also adds more synthetic traffic patterns.
2016-10-06ruby: rename ALPHA_Network_test protocol to Garnet_standalone.Tushar Krishna
Over the past 6 years, we realized that the protocol is essentially used to run the garnet network in a standalone manner, and feed standard synthetic traffic patterns through it.
2016-10-04kvm: Adding details to kvm page fault in x86Alexandru Dutu
Adding details, e.g. rip, rsp etc. to the kvm pagefault exit when in SE mode.
2016-10-04misc: Adds a warning in case gdb is attached multiple timesAlexandru Dutu
Instead of scheduling another event, this patch adds a warning in case gdb is attached multiple times and the first attachement event has not been processed yet.
2016-10-04gpu-compute: Added method to compute the actual workgroup sizeAlexandru Dutu
This patch adds a method to the Wavefront class to compute the actual workgroup size. This can be different from the maximum workgroup size specified when launching the kernel through the NDRange object. Current solution is still not optimal, as we are computing these for each wavefront and the dispatcher also needs to have this information and can't actually call Wavefront::computeActuallWgSz before the wavefronts are being created. A long term solution would be to have a Workgroup class that deals with all these details.
2016-10-04config: Fix lat_mem_rd example scriptAndreas Hansson
Adjust the traffic generator time-out so that the script works out of the box Change-Id: I6b3b6b11f98b094ae3acdbe09488c26e4aeb0ab4 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
2016-10-04sim: Add a checkpoint function to test for entriesAndreas Sandberg
When loading a checkpoint, it's sometimes desirable to be able to test whether an entry within a secion exists. This is currently done automatically in the UNSERIALIZE_OPT_SCALAR macro, but it isn't possible to do for arrays, containers, or enums. Instead of adding even more macros, add a helper function (CheckpointIn::entryExists()) that tests for the presence of an entry. Change-Id: I4b4646b03276b889fd3916efefff3bd552317dbc Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
2016-09-29ruby: correct size for partial memory writesBrad Beckmann
Fixed AbstractController::queueMemoryWritePartial to specify the correct size for partial memory writes.
2016-09-29mem: minor dprintf fix to abstract memBrad Beckmann
print number of bytes written as a decimal number, not hex
2016-09-22arm: disable GIC extensionsCurtis Dunham
Change-Id: If19b9c593b48ded1ea848f2d3710d4369ec8a221 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
2016-09-22tests, arm: Reinstate accidentally removed switcheroo testsAndreas Sandberg
Two of the switcheroo tests were accidentally removed due to unexpected Mercurial behavior. Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
2016-09-22cpu: Fix the O3 CPU DrainRekai Gonzalez-Alberquilla
The drain did not wait until stages were ready again. Therefore, as a result of messages in the TimeBuffer being drain, the state after the drain was not consistent and asserts fired in some places when the draining happened after a stage got blocked, but before the notification arrived to the previous stages. Change-Id: Ib50b3b40b7f745b62c1eba2931dec76860824c71 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
2016-09-22test: Make the memtest and memcheck tests functional onlyAndreas Sandberg
The memtest and memcheck are not designed to test timing. Make them functional only to make ref diffs less noisy in the future. Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
2016-09-22tests: Make remaining switcheroo tests functional onlyAndreas Sandberg
The switcheroo tests only really serve to check functional correctness. Checking for stat differences in them just increases the size of reference diffs. Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
2016-09-20ext: update SST test configCurtis Dunham
Align configuration with new SST change [1] requiring units for memHierarchy's backend.mem_size parameter. [1] https://github.com/sstsimulator/sst-elements/commit/c901abb4e79644ff18f5222c94f5dae012772e1e Change-Id: I19fa09bec8aa453dc52d154598a4ebb20ea304d8
2016-09-16gpu-compute: fix typo in GPUDispatcherTony Gutierrez
2016-09-16hsail: Fix disassembly of load instruction with 3 destination operandsAlexandru Dutu
2016-09-16gpu-compute: Adding context serialization methods to WavefrontAlexandru Dutu
This patch adds methods to serialize the context of a particular wavefront to the simulated system memory. Context serialization is used when a wavefront is preempeted (i.e. context switch).
2016-09-16gpu-compute: Refactoring Wavefront::dynWaveIdAlexandru Dutu
2016-09-16gpu-compute: Adding vector register file debug messagesAlexandru Dutu
This patch introduces DPRINTFs for reading and writing to and from the vector register file.
2016-09-16gpu-compute: Changing reconvergenceStack typeAlexandru Dutu
std::stack has no iterators, therefore the reconvergence stack can't be iterated without poping elements off. We will be using std::list instead to be able to iterate for saving and restoring purposes.
2016-09-16gpu-compute: Adding ioctl for HW context sizeAlexandru Dutu
Adding runtime support for determining the memory required by a SIMD engine when executing a particular wavefront.
2016-09-16gpu-compute: Wavefront refactoringAlexandru Dutu
Renaming members of the Wavefront class in accordance with the style guide.
2016-09-16gpu-compute: Remove WFContextAlexandru Dutu
WFContext struct is currently unused and it has been rendered not useful in saving and restoring the context of a Wavefront. Wavefront class should be sufficient for that purpose and the runtime can figure out the memory size it will need to allocate for a Wavefront through an IOCTL.
2016-09-16tests, arm: Make switcheroo and checkpoint tests functionalAndreas Sandberg
Switcheroo and checkpoint tests should generally be considered to be successful if they run to completion. Remove all reference output files from the switcheroo and checkopint tests to make them purely functional. Change-Id: I70b47853bd662b7a33716d9e0d2154b16077f9dc Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Curtis Dunham <curtis.dunham@arm.com>
2016-09-16tests: Add support for functional only testsAndreas Sandberg
Modify the ClassicTest class to only emit a stat verification test unit if there is a reference stat file. This makes it possible to design tests that don't care about stat changes. To generate purely functional tests, we need to be able to create empty test reference directories. This does not work well with many revision control systems. As a workaround, add a file named EMPTY to the list of ignored files in the test harness. This file can be used as a placeholder in otherwise empty test directories. Change-Id: I583c8c4e55479f0d48fa99d0b0d1eac9221e6652 Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Curtis Dunham <curtis.dunham@arm.com>
2016-09-15base: eliminate ipython warningCurtis Dunham
Change-Id: I3e282baeb969b6bb9534813a2f433d68246c0669 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
2016-09-15arm: Add m5_fail support for aarch64Ricardo Alves
Change-Id: Id2acbc09772be310a0eb9e33295afab07e08a4fa Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
2016-09-15cpu: Support exit when any one Trace CPU completes replayRadhika Jagtap
This change adds a Trace CPU param to exit simulation early, i.e. when the first (any one) trace execution is complete. With this change the user gets a choice to configure exit as either when the last CPU finishes (default) or first CPU finishes replay. Configuring an early exit enables simulating and measuring stats strictly when memory-system resources are being stressed by all Trace CPUs. Change-Id: I3998045fdcc5cd343e1ca92d18dd7f7ecdba8f1d Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
2016-09-15cpu: Adjust for trace offset and fix statsRadhika Jagtap
This change subtracts the time offset present in the trace from all the event times when nodes and request are sent so that the replay starts immediately when the simulation starts. This makes the stats accurate when the time offset in traces is large, for example when traces are generated in the middle of a workload execution. It also solves the problem of unnecessary DRAM refresh events that would keep occuring during the large time offset before even a single request is replayed into the system. Change-Id: Ie0898842615def867ffd5c219948386d952af7f7 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
2016-09-15cpu: Add frequency scaling to the Trace CPURadhika Jagtap
This change adds a simple feature to scale the frequency of the Trace CPU. The compute delays in the input traces provide timing. This change adds a freqency multiplier parameter to the Trace CPU set to 1.0 by default. The compute delay is manipulated to effectively achieve the frequency at which the nodes become ready and thus scale the frequency of the Trace CPU. Change-Id: Iaabbd57806941ad56094fcddbeb38fcee1172431 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
2016-09-15arm, config: Fixups for the example big.LITTLE(tm) configurationGabor Dozsa
This patch refactors the configuration file to use a more object-oriented design. Change-Id: I44ac2d063c2b5901f385544fb6ce3f259459cb05 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Gabor Dozsa <gabor.dozsa@arm.com>
2016-09-13kvm: Support timing accesses for KVM cpuMichael LeBeane
This patch enables timing accesses for KVM cpu. A new state, RunningMMIOPending, is added to indicate that there are outstanding timing requests generated by KVM in the system. KVM's tick() is disabled and the simulation does not enter into KVM until all outstanding timing requests have completed. The main motivation for this is to allow KVM CPU to perform MMIO in Ruby, since Ruby does not support atomic accesses.
2016-09-13x86: Force strict ordering for memory mapped m5opsMichael LeBeane
Normal MMAPPED_IPR requests are allowed to execute speculatively under the assumption that they have no side effects. The special case of m5ops that are treated like MMAPPED_IPR should not be allowed to execute speculatively, since they can have side-effects. Adding the STRICT_ORDER flag to these requests blocks execution until the associated instruction hits the ROB head.
2016-09-13sim: Refactor quiesce and remove FS assertsMichael LeBeane
The quiesce family of magic ops can be simplified by the inclusion of quiesceTick() and quiesce() functions on ThreadContext. This patch also gets rid of the FS guards, since suspending a CPU is also a valid operation for SE mode.
2016-09-13config: move dist-gem5 options to common configMichael LeBeane
dist-gem5 should not be restricted to FullSystem mode.
2016-09-13dev: Add a DmaCallback class to DmaDeviceMichael LeBeane
This patch introduces the DmaCallback helper class, which registers a callback to fire after a sequence of (potentially non-contiguous) DMA transfers on a DmaPort completes.
2016-09-13sim, syscall_emul: Add mmap to EmulatedDriverMichael LeBeane
Add support for calling mmap on an EmulatedDriver file descriptor.
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