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gem5
hitsb
invisispec-1.0
invisispec-with-dift
is-ift
is-ift-cachehit
is-rebase
is-rebase-new
is-rebase-new2
is-rebase-new3-rdtscp
is-rebase04-linux3.2
is-rebase05
is-rebase06-RequestPtr
is-rebase07-GCC8
is-rebase08-QoSmem
is-rebase09-linuxarm-3.7.0
is-rebase10-DynInstPtr
is-rebase11-LSQUnit
is-rebase12
simple-object-demo
gem5
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Author
2007-07-18
Fix a compilation error for SubBitUnions,
Gabe Black
2007-07-18
Implement the x86 nop to be a "fault" microop which returns "NoFault".
Gabe Black
2007-07-18
Add a generateDisassembly function to the MicroFault StaticInst.
Gabe Black
2007-07-18
Make name, isMachineCheckFault, and isAlignmentFault const.
Gabe Black
2007-07-17
Calculate the correct address size.
Gabe Black
2007-07-17
Make disassembled x86 register indices reflect their size.
Gabe Black
2007-07-17
Implemented jnz.
Gabe Black
2007-07-17
Use limm to set up immediate value for subtract instruction.
Gabe Black
2007-07-17
Implement the jz instruction.
Gabe Black
2007-07-17
Make "test" set some condition codes.
Gabe Black
2007-07-17
Add in support for condition code flags.
Gabe Black
2007-07-17
Add in operand which holds the condition code bits of the flag register.
Gabe Black
2007-07-17
Add symbols for each of the flags a microop could set and each condition it c...
Gabe Black
2007-07-17
Actually include miscregs.hh
Gabe Black
2007-07-17
Create a file to describe misc registers.
Gabe Black
2007-07-17
Create a file of functions for computing condition codes.
Gabe Black
2007-07-17
Add a spot for the condition code portion of the flag register.
Gabe Black
2007-07-17
Add a conversion constructor so a bitunion can be initialized to a value.
Gabe Black
2007-07-17
Make sure responses never get blocked.
Steve Reinhardt
2007-07-17
Forward cache-to-cache responses through other caches.
Steve Reinhardt
2007-07-17
Assert that an mshr has a target in getTarget().
Steve Reinhardt
2007-07-15
Fix bug with timing snoop upcalls to MemTest object.
Steve Reinhardt
2007-07-15
Add valgrind-suppressions file.
Steve Reinhardt
2007-07-15
Merge from head.
Steve Reinhardt
2007-07-15
Fix up a bunch of multilevel coherence issues.
Steve Reinhardt
2007-07-15
Make Bus::findPort() a little more useful.
Steve Reinhardt
2007-07-15
Fix problem with unset max_loads in memtest.
Steve Reinhardt
2007-07-15
Punt on old -n/-c memtest args.
Steve Reinhardt
2007-07-15
Add --force-bus option to memtest.py.
Steve Reinhardt
2007-07-14
New tree-based algorithm for creating more complex cache hierarchies.
Steve Reinhardt
2007-07-14
Handle broken swig version that prints version info on stderr.
Steve Reinhardt
2007-07-14
Move bitunion code into it's own file.
Gabe Black
2007-07-14
Pull some hard coded base classes out of the isa description.
Gabe Black
2007-07-14
Add CacheRepl trace flag and move a couple DPRINTFs to it.
Steve Reinhardt
2007-07-14
Move a couple of DPRINTFs from Cache to CachePort.
Steve Reinhardt
2007-07-14
Fix bug in copying packet with static data pointer.
Steve Reinhardt
2007-07-14
Merge from head.
Steve Reinhardt
2007-07-14
Disable PrintThreadInfo since it causes a panic when using VPtr.
Steve Reinhardt
2007-07-14
Make NO_FAST_ALLOC compile.
Steve Reinhardt
2007-07-14
Merge of DPRINTF fixes from head.
Steve Reinhardt
2007-07-14
Fix & tweak DPRINTFs for tracediff w/new cache code.
Steve Reinhardt
2007-07-14
Merge in .hgignore from head.
Steve Reinhardt
2007-07-13
Merge with head
Steve Reinhardt
2007-07-13
ignore stuff that we don't want to see in the status
Nathan Binkert
2007-07-13
transfer tags
Nathan Binkert
2007-07-03
Delete packets when we're done with them.
Steve Reinhardt
2007-07-02
Couple more minor bug fixes for FS timing mode.
Steve Reinhardt
2007-07-02
Fix a couple LL/SC bugs that only affected timing mode.
Steve Reinhardt
2007-07-02
bus.cc:
Steve Reinhardt
2007-06-30
Make CPU models use new LoadLockedReq/StoreCondReq commands.
Steve Reinhardt
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