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2019-01-14config: Fix an error message in Port.splice().Gabe Black
That error message referenced non-existent variables which were likely renamed without updating the error message. Change-Id: I6878802ef4b83e3fdf75a860d848b8c5e2e8d6c0 Reviewed-on: https://gem5-review.googlesource.com/c/15515 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2019-01-11scons: added support of default Python installation on MacOSAndrea Mondelli
Recent MacOS versions are distributed with python 2.7. This version of python is sufficient to compile and run gem5. This patch allows to use the default python instead of the version provided by third-party tools (e.g., brew) The default MacOS LLDB debugger is linked against the default python installation, which conflicts with Python framework provided by third-party package systems. This patch removes the need of gem5 to have multiple python installations on MacOS, if not explicitly installed. Change-Id: I98f24804149cb2e04ca432c66d2f57e0296af7b2 Reviewed-on: https://gem5-review.googlesource.com/c/15475 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2019-01-11misc: updated shabang for python scriptAndrea Mondelli
The default python on MacOS doesn’t have an alias to python2. The official python version supported in gem5 is Python2.7. This patch updates the shabang according to the version required in gem5. Change-Id: I9533c0f7858b5b3cab0ef101be1ee5cd718105b0 Reviewed-on: https://gem5-review.googlesource.com/c/15375 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
2019-01-10sim-se, arch-arm: Add support for getdents64Javier Setoain
Change-Id: Ib27950144d4c9802ffb842db98aec9e433ccbfc5 Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Cc: Giacomo Travaglini <giacomo.travaglini@arm.com> Cc: Javier Setoain <javier.setoain@arm.com> Cc: Brandon Potter <Brandon.Potter@amd.com> Reviewed-on: https://gem5-review.googlesource.com/c/15438 Maintainer: Brandon Potter <Brandon.Potter@amd.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
2019-01-10arch-arm, sim-se: Add support for TLS in cloneAndreas Sandberg
Change-Id: I1f78dce05a48a2e3adfaf027cd38ab55507b9611 Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Cc: Giacomo Travaglini <giacomo.travaglini@arm.com> Cc: Javier Setoain <javier.setoain@arm.com> Cc: Brandon Potter <Brandon.Potter@amd.com> Reviewed-on: https://gem5-review.googlesource.com/c/15437 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Brandon Potter <Brandon.Potter@amd.com>
2019-01-10arch-arm, sim-se: Fix incorrect SP handling in cloneAndreas Sandberg
The clone syscall is currently broken on aarch64 since the aarch64 code uses an incorrect SP register. Fix this by storing the new stack pointer in SP_EL0 instead of R13. Change-Id: Ie17990b4f359608e3b53e5bf625eca53769a6653 Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Cc: Giacomo Travaglini <giacomo.travaglini@arm.com> Cc: Javier Setoain <javier.setoain@arm.com> Cc: Brandon Potter <Brandon.Potter@amd.com> Reviewed-on: https://gem5-review.googlesource.com/c/15436 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Brandon Potter <Brandon.Potter@amd.com>
2019-01-10sim-se: Refactor clone to avoid most ifdefsAndreas Sandberg
Some parts of clone are architecture dependent. In some cases, we are able to use architecture-specific helper functions or register aliases. However, there is still some architecture-specific that is protected by ifdefs in the common clone implementation. Move these architecture-specific bits to the architecture-specific OS class instead to avoid these ifdefs and make the code a bit more readable. Change-Id: Ia0903d738d0ba890863bddfa77e3b717db7f45de Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Cc: Giacomo Travaglini <giacomo.travaglini@arm.com> Cc: Javier Setoain <javier.setoain@arm.com> Cc: Brandon Potter <Brandon.Potter@amd.com> Reviewed-on: https://gem5-review.googlesource.com/c/15435 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Brandon Potter <Brandon.Potter@amd.com>
2019-01-10sim-se: Correctly calculate next PC in cloneAndreas Sandberg
The clone syscall doesn't propagate all state in the PCState object when calculating the return PC of a newly created process. Instead of creating a new PCState object from the next PC address, copy the old PC and advance it. Change-Id: Ice53831920bcb5d198865169ed2cca8d06e37cfe Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Cc: Giacomo Travaglini <giacomo.travaglini@arm.com> Cc: Javier Setoain <javier.setoain@arm.com> Cc: Brandon Potter <Brandon.Potter@amd.com> Reviewed-on: https://gem5-review.googlesource.com/c/15417 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Brandon Potter <Brandon.Potter@amd.com>
2019-01-10sim-se: Use CONFIG_CLONE_BACKWARDS for ArmAndreas Sandberg
Linxu on Arm users the CLONE_BACKWARDS argument order for the clone syscall. Change-Id: I48deb4f03140c9d4ef7a89e3e33813e76777f999 Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Cc: Giacomo Travaglini <giacomo.travaglini@arm.com> Cc: Javier Setoain <javier.setoain@arm.com> Cc: Brandon Potter <Brandon.Potter@amd.com> Reviewed-on: https://gem5-review.googlesource.com/c/15416 Reviewed-by: Brandon Potter <Brandon.Potter@amd.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Brandon Potter <Brandon.Potter@amd.com>
2019-01-10arch-arm, sim-se: Wire up syscalls needed for pthreadsJavier Setoain
Change-Id: I8da5e3e0d7dc5d31ac82ed2045109d6d73cbf99d Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Cc: Giacomo Travaglini <giacomo.travaglini@arm.com> Cc: Javier Setoain <javier.setoain@arm.com> Cc: Brandon Potter <Brandon.Potter@amd.com> Reviewed-on: https://gem5-review.googlesource.com/c/15415 Reviewed-by: Brandon Potter <Brandon.Potter@amd.com> Maintainer: Brandon Potter <Brandon.Potter@amd.com>
2019-01-10dev-arm: Add a VExpress_GEM5_V2 platform with GICv3 supportJairo Balart
Change-Id: I6fd14138d94654e8e60cde08239ea9a50fc19eb7 Reviewed-on: https://gem5-review.googlesource.com/c/14255 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
2019-01-10dev-arm: Add a GICv3 modelJairo Balart
Change-Id: Ib0067fc743f84ff7be9f12d2fc33ddf63736bdd1 Reviewed-on: https://gem5-review.googlesource.com/c/13436 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
2019-01-10base: Make it possible to convert strings to enumsGiacomo Travaglini
The __to_number helper function defined in base/str.hh is used by unserializing code. Its purpose is to convert a string into an integral/floating point number. Since enums underlying type can only be an integer type, it makes sense to extend the helper function for enums as well. In this way it will be possible to unserialize Enums and containers of Enums without the need of casting. Change-Id: I74069cc4c04ec8b5eb80939acea7ab18fb366dd4 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Ciro Santilli <ciro.santilli@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/15336 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2019-01-10systemc: Fix a function which was broken during style fixes.Gabe Black
Some brackets were misapplied while correcting the style of the TLM header files. Change-Id: I4e26d0316ca2545a5f26ad5fef0e986e42a1895b Reviewed-on: https://gem5-review.googlesource.com/c/15455 Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com> Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>
2019-01-09arch-arm: Additional bits in misc ARM registers to use with the TLB and page ↵Ivan Pizarro
walker Change-Id: I71a6360709b35ad788d8c88fba1a7a2761233dbd Reviewed-on: https://gem5-review.googlesource.com/c/14555 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2019-01-09systemc: Make input.txt a dependency for the tlm/endian_conv test.Gabe Black
This input file is consumed by the test and needs to be in the build directory. Change-Id: I3420dec9e41a1981c7d4e6df47f03273e378ab66 Reviewed-on: https://gem5-review.googlesource.com/c/15064 Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com> Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>
2019-01-09systemc: Exclude some failing systemc TLM tests in working.filt.Gabe Black
These are known to fail and are undiagnosed, and so are not "working" and shouldn't be in included when using the working.filt filter file. Change-Id: I46e9f880bd4095085e4217ac6bec950cb2af9536 Reviewed-on: https://gem5-review.googlesource.com/c/15066 Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com> Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>
2019-01-09systemc: Remove the TLM dependence on a non-standard method.Gabe Black
The sc_event_finder class in Accellera's implementation has a non-standard report_error function that it uses internally. The TLM headers were calling that function in their own event finder subclass. This change replaces that call with what should be an equivalent bit of code which is based on the report_error implementation. Change-Id: Id57d26791df01403a77e70d5f4a00f650dc33599 Reviewed-on: https://gem5-review.googlesource.com/c/15063 Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com> Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>
2019-01-09systemc: Stop using the sc_string_view type.Gabe Black
It doesn't seem to provide anything more that std::string, and comes with extra dependencies/baggage. Change-Id: I2c599bcc93fa4a944ff249410d24e8f8be981afe Reviewed-on: https://gem5-review.googlesource.com/c/15298 Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com> Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>
2019-01-09systemc: Replace sc_core::sc_type_index with std::type_index.Gabe Black
The former is either the same as the later, or a custom wrapper if C++11 isn't supported. Since we generally expect C++11 support, we can skip the indirection. Change-Id: I9a45e3854bb7cc56d094e3fe2773fe4b5c94403b Reviewed-on: https://gem5-review.googlesource.com/c/15297 Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com> Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>
2019-01-09systemc: Stop using the Accellera specific "none" global event object.Gabe Black
That event being available is nonstandard. Define our own static event for use in that case. Change-Id: I5e8892bd83cc1984d63949ef3e249755dca0c702 Reviewed-on: https://gem5-review.googlesource.com/c/15296 Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com> Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>
2019-01-09systemc: Rename tlm_core header files to have a .hh extentension.Gabe Black
This makes those files more consistent with other headers in gem5. The top level headers (tlm and tlm.h) and the tlm_utils headers were left alone since the user might reasonably expect those to have a well known name. The tlm_core headers by comparison are an implementation detail, and users shouldn't include them directly by name. Change-Id: Ibc82e8159e47717c79d76f50ed96fdd619294a06 Reviewed-on: https://gem5-review.googlesource.com/c/15067 Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com> Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>
2019-01-09systemc: Add a dummy argv[0] when running the tests.Gabe Black
One TLM test will complain if argc isn't 1 or 2, assuming that that must mean that argc > 2. If it's 0 then the test will also complain and fail. We therefore need to pass it at least a dummy value in argv/argc. Change-Id: I5c64856f46d1459d7238e88ad8ba06933c7c38b8 Reviewed-on: https://gem5-review.googlesource.com/c/15065 Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com> Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>
2019-01-09systemc: Stop using the non-standard sc_time % in TLM.Gabe Black
The TLM headers were using the non-standard % operator on sc_time. This change replaces that with % applied to the result of sc_time::value(). Change-Id: Ic381eb1ada2c994d04e65896db178f58446944ae Reviewed-on: https://gem5-review.googlesource.com/c/15062 Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com> Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>
2019-01-09systemc: Add an elaboration_done method to sc_simcontext.Gabe Black
The TLM headers rely on this non-standard function. Change-Id: Iaedec35f1f363dcf3e1fcdb58a74eb2cdc05ddc0 Reviewed-on: https://gem5-review.googlesource.com/c/15061 Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com> Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>
2019-01-09systemc: Include cstring in the tlm header file.Gabe Black
A lot of TLM implementation assumes the string functions (memcpy, memset, etc) are available, but don't include cstring. Lets do that for them to avoid having to fix up a lot of places. Change-Id: I1f26d3a227fe2cefc2613e24cbb0333216e46ee9 Reviewed-on: https://gem5-review.googlesource.com/c/15060 Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com> Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>
2019-01-09systemc: Remove redundant tlm_ prefixes from file names.Gabe Black
We already know those files belong to tlm because of the directory they're in. Removing the prefix makes the paths of the headers less enormously long. Change-Id: I869e58fae904162f353bb31f4c0919fba08dffa6 Reviewed-on: https://gem5-review.googlesource.com/c/15059 Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com> Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>
2019-01-09systemc: Replace some calls to some Accellera specific functions in TLM.Gabe Black
The TLM event finder class was calling implementation specific functions from the Accellera version of systemc. This change replaces those calls with equivalent calls which match the gem5 implementation. Change-Id: I0ecdb0a4bf09aeb1aad823a01105fbd88edb4601 Reviewed-on: https://gem5-review.googlesource.com/c/15075 Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com> Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>
2019-01-09systemc: Rename tlm .cpp files to .cc and add SConscripts.Gabe Black
Change-Id: Ia30192b441dd34bc7165c6335386c88c0015fdf6 Reviewed-on: https://gem5-review.googlesource.com/c/15295 Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com> Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>
2019-01-09systemc: Fix style issues in the TLM header files.Gabe Black
Change-Id: Id12ffb9b56b3887afcf30120f81ce5eb75a5987b Reviewed-on: https://gem5-review.googlesource.com/c/15057 Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com> Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>
2019-01-09systemc: Also look for tests in the tlm test directory.Gabe Black
Both basic systemc and tlm tests were present, but scons only looked in the systemc directory when populating the test json. This change makes it also look in the tlm directory so that those tests can be run. Change-Id: Id65b744664350f6105fb3a4f28cbc7ab91d8c82e Reviewed-on: https://gem5-review.googlesource.com/c/15056 Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com> Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>
2019-01-09systemc: Initial import of TLM headers from Accellera.Gabe Black
These headers will need to be cleaned up and have some Accellera specific quirks ironed out of them, but I'll do that in a later change to make it clear what those changes are. Change-Id: Ia4e08633ab552b4c616c66c9b7e2bbd78ebfe7b9 Reviewed-on: https://gem5-review.googlesource.com/c/15055 Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com> Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>
2019-01-07system-arm: Add device tree for new VExpress GEM5_V2 platformJairo Balart
Change-Id: Ifc2b91afe5b88a656b4ed1c64ab6cca97f082034 Reviewed-on: https://gem5-review.googlesource.com/c/14275 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2019-01-07system-arm: Add aarch64 bootloader support for GICv3Jairo Balart
Change-Id: If75262709868cc59d320f60273a32397339f1dd5 Signed-off-by: Jairo Balart <jairo.balart@metempsy.com> Reviewed-on: https://gem5-review.googlesource.com/c/13435 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2019-01-07scons: Disable partial linking on Mac OSNikos Nikoleris
Up until Apple LLVM version 10.0.0 (clang-1000.11.45.5), partial linked objects do not expose symbols that are marked with the hidden visibility and consequently building gem5 on Mac OS fails. As a workaround, we disable partial linking, however, we may want to revisit in the future. Change-Id: I0a26dae082bf723c2bd49d90e4497e44ecab9c41 Signed-off-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/15235 Reviewed-by: Andrea Mondelli <andrea.mondelli@ucf.edu> Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com>
2019-01-04dev, arm: Warn on PL011 DMA disableJan-Peter Larsson
The PL011 spec specifies a DMACR register at offset 0x48, which isn't implemented in the model. Currently any attempt to access the register results in a panic. This change swaps the panic for a warning only when software writes into DMACR to disable DMA, keeping the panic otherwise. Change-Id: I04586b52df8d5d174536276fd7ae19e77ff4681a Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/15279 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2019-01-04dev-arm: Added VGIC GICV_IIDR responseAnouk Van Laer
Change-Id: I60e8eadbbbf07c0f8b726213fd580aeb0dd0e00b Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Anouk Van Laer <anouk.vanlaer@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/15278 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2019-01-04dev-arm: Implement GIC-400 model from GicV2Giacomo Travaglini
Implementation registers for the GICv2 model currently hold values referring to a GIC-400 implementation. This patch is making them parametrizable so that it is possible to instantiate a GIC-400 model. The patch is also modifying Realview platform to use new GIC-400 model in lieau of GICv2. Change-Id: I446db8c796ee3c2708af91e9139f0a6e7947321b Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/15277 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2019-01-04dev-arm: Move VGic from Realview.py to Gic.pyGiacomo Travaglini
Change-Id: I17f2fb6be2435d4601263e7f68a0582e0cc70838 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/15276 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2019-01-04dev-arm: Added unimplemented GICv2 GICC_DIRAnouk Van Laer
This GICC CPU register is not implemented but just gives a warning. Change-Id: I7630aa1df78dde5cf84a87e26cd580b00b283673 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Anouk Van Laer <anouk.vanlaer@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/15275 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2019-01-03arm: properly handle RES0/1 for SCTLRsCurtis Dunham
They were being treated as RAZ/RAO, which is incorrect. Put the access masks in the register metadatabase now that we have one. Also fix this for HVBAR. Change-Id: I097c847e35be2d59fb8235fc621bb061ef514cfb Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/10401 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-12-22cpu: Stop using unions to store FP registers.Gabe Black
These are now accessed only as integer values. Change-Id: I21ae6537ebbcbaa02890384194ee1ce001c092bb Reviewed-on: https://gem5-review.googlesource.com/c/14458 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Gabe Black <gabeblack@google.com>
2018-12-20arch, cpu: Remove float type accessors.Gabe Black
Use the binary accessors instead. Change-Id: Iff1877e92c79df02b3d13635391a8c2f025776a2 Reviewed-on: https://gem5-review.googlesource.com/c/14457 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Gabe Black <gabeblack@google.com>
2018-12-19arch-arm: Add Crypto in SE modeGiacomo Travaglini
This patch is also enabling AArch32 crypto instructions by setting the ID_ISAR5 register accordingly. Change-Id: Id412585b39b78570a65bd3047199c84e9db76cda Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/15155 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-12-19systemc: Allow specific functions to shadow the base class methodNikos Nikoleris
sc_in::bind and sc_core::sc_object::print shadow their respective base class method. This change adds the necessary declarations to inform the compiler that this is intentional. Change-Id: I8c6bc0f05aa568630783db63d52be90f4ea4748c Signed-off-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/15135 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com>
2018-12-19scons: Disable systemc on Mac OSNikos Nikoleris
LLVM on Mac OS up until version 10.0.0 doesn't seem to support the attribute for weak linking and fails to compile. Additionally, even the basic example tests fail. Therefore, this change disables systemc by default on Mac OS until we address these issues. Change-Id: Iaa6360ec61317e01f4e645af8b509961b3144282 Signed-off-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/14818 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com>
2018-12-18arch: Make the ISA parser always use binary floating point accessors.Gabe Black
Any operands which use read_code or write_code would need to start using the floatToBits and bitsToFloat, but only ARM is using that mechanism, and not on float operands. Also I notice that the "predicate" mechanism for operands ignores the read_code and write_code mechanism, and using both will not work correctly. This change makes no attempt to fix that problem, but shouldn't contribute to it either. Change-Id: I0e3a7f78ed28f40cb66958ef12c32e862950fde0 Reviewed-on: https://gem5-review.googlesource.com/c/14456 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Brandon Potter <Brandon.Potter@amd.com> Maintainer: Gabe Black <gabeblack@google.com>
2018-12-18systemc: Ensure resets and edges are notified when signaling a change.Gabe Black
Boolean sc_buffers (either pure bool or sc_dt::sc_logic) should signal positive and negative edges and resets even when their value doesn't change, unlike sc_signals. The spec doesn't actually say that and just mentions the value changed event, but it may have been implied that the other types of events also happen, they just made special mention of the value change event. This change moves some code around a bit so that when _signalChange() is called, if the underlying type is a boolean signal, it will automatically notify the appropriate edge event and signal any reset. Putting the functionality in _signalChange instead of delegating it to the sc_buffer lets us have a single template for sc_buffer and makes the base class template specialization handle whether the edge events exist, and if so which should be notified. Change-Id: Ic4ca86afc3fde6a9df5c15a0a7386e24ac89a9e2 Reviewed-on: https://gem5-review.googlesource.com/c/14916 Reviewed-by: Matthias Jung <jungma@eit.uni-kl.de> Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com>
2018-12-11cpu: Fixed typos in parameter/stats descriptionsPau Cabre
Change-Id: I7b3274a3e37128da35f497da150af08343e97ee6 Signed-off-by: Pau Cabre <pau.cabre@metempsy.com> Reviewed-on: https://gem5-review.googlesource.com/c/14795 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Ilias Vougioukas <ilias.vougioukas@arm.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2018-12-11cpu: Added parameters to enable/disable features in LTAGEPau Cabre
They are for the following features in the LTAGE loop predictor: - Hashing for calculating the loop table entry - Add direction information - Add speculative iteration number information Change-Id: I395f4526163ee0d0229d1e87cde2bb046f1dd43a Signed-off-by: Pau Cabre <pau.cabre@metempsy.com> Reviewed-on: https://gem5-review.googlesource.com/c/14597 Reviewed-by: Ilias Vougioukas <ilias.vougioukas@arm.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Louis Delhez <ldelhez@ucla.edu> Maintainer: Jason Lowe-Power <jason@lowepower.com>
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