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2019-03-20attack code and exp scriptis-rebase12Iru Cai
2019-03-20invisispec-1.0 configsIru Cai
2019-03-20invisispec-1.0 sourceIru Cai
2019-01-23arch-arm: Implement LoadAcquire/StoreRelease in AArch32Giacomo Travaglini
This patch is implementing LoadAcquire/StoreRelease instructions in AArch32, which were added in ARMv8-A only and where not present in ARMv7. Change-Id: I5e26459971d0b183a955cd7b0c9c7eaffef453be Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/15817 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2019-01-23arch-arm: IsStoreConditional flag set depending on flavorGiacomo Travaglini
This patch is aligning A32 with A64 where the IsStoreConditional flag doesn't have to be specified manually in the instruction implementation, but will be automatically added to any exclusive store. Change-Id: Id02ed6fc2beeca6d125017393714a7c6eb3d8a33 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/15816 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2019-01-23arch-arm: Remove SWP and SWPB instructionsGiacomo Travaglini
The SWP and SWPB instructions have been removed from AArch32. It was previously (ARMv7) possible to enable them with the ID_ISAR0.Swap bits, which are now hardcoded to 0b0000 (SWP and SWPB not implemented) Change-Id: Ic32b534454a7e0f7494a6f0b5e11182c65b3fe24 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/15815 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2019-01-23systemc: Fix TLM related includes.Gabe Black
There are a couple things this CL fixes related to the TLM #includes. 1. Removes #includes of <systemc> and <tlm>. These bring in a header file from boost which shouldn't be necessary but which some of the tests (and likely some external code) depends on. We avoid including those in files built into gem5 itself so that gem5 isn't dependent on boost. 2. All includes in ext should be relative. That way those headers can be removed from gem5 and still build, allowing them to be moved over to or referenced from a foreign codebase which isn't part of gem5. Change-Id: I76e267385b48cb4fe93aea89ec8319c76465a0a4 Reviewed-on: https://gem5-review.googlesource.com/c/15796 Reviewed-by: Ciro Santilli <ciro.santilli@arm.com> Maintainer: Gabe Black <gabeblack@google.com>
2019-01-23arm: Replace MiscReg with RegVal in utility.(hh|cc).Gabe Black
These uses snuck in after the previous pass which made this switch in the rest of these files. Change-Id: Ie891c6ec393a65f1c57c54301f0a2bb920d38bb0 Reviewed-on: https://gem5-review.googlesource.com/c/15795 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com>
2019-01-23mem-ruby: Fix missing TBE allocation and deallocationZicong Wang
The TBE allocation and deallcation are currently missing during the directory state transition from I to M in protocol MI_example. Change-Id: If7569c02faf56ea84c34ee1345f1a33d318cdfff Signed-off-by: Zicong Wang <wangzicong@nudt.edu.cn> Reviewed-on: https://gem5-review.googlesource.com/c/15535 Reviewed-by: Pouya Fotouhi <pfotouhi@ucdavis.edu> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2019-01-22sparc: Get rid of some register type definitions.Gabe Black
These are IntReg, FloatReg, FloatRegBits, and MiscReg. These have been supplanted by the global types RegVal and FloatRegVal. Change-Id: I956abfc7b439b083403e1a0d01e0bb35020bde44 Reviewed-on: https://gem5-review.googlesource.com/c/13627 Maintainer: Gabe Black <gabeblack@google.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
2019-01-22arch: cpu: Stop passing around misc registers by reference.Gabe Black
These values are all basic integers (specifically uint64_t now), and so passing them by const & is actually less efficient since there's a extra level of indirection and an extra value, and the same sized value (a 64 bit pointer vs. a 64 bit int) is being passed around. Change-Id: Ie9956b8dc4c225068ab1afaba233ec2b42b76da3 Reviewed-on: https://gem5-review.googlesource.com/c/13626 Maintainer: Gabe Black <gabeblack@google.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
2019-01-22arm: Get rid of some register type definitions.Gabe Black
These are IntReg, FloatReg, FloatRegBits, and MiscReg. These have been supplanted by the global types RegVal and FloatRegVal. Change-Id: Ief1cd85d0eff7156282ddb1ce168a2a5677f7435 Reviewed-on: https://gem5-review.googlesource.com/c/13625 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
2019-01-22arm: dev: Replace ArmISA::MiscReg with RegVal in the GIC v3 model.Gabe Black
Other dev code was already switched over. This code was written before the switch over (or unaware of it), and checked in after. Change-Id: Ibb9e9e4300d01cc46e4dae668274debc2a4989ba Reviewed-on: https://gem5-review.googlesource.com/c/15755 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2019-01-22arch-arm: implement the GDB XML target description for ARMCiro Santilli
The supported registers are essentially the same as before this patch, but it is now trivial to make new registers visible in future commits. Change-Id: Id15b7aeccca824c342e49a626d2877179474f3d4 Reviewed-on: https://gem5-review.googlesource.com/c/15138 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2019-01-22ext: import GDB XML target description files for armCiro Santilli
The XML files were copied from the binutils-gdb source tree under gdb/features at tag gdb-8.2-release Those XML files have a different copyright header than the rest of binutils-gdb which allows them to be copied into non-GPL projects. Change-Id: I49bdeaad91ceb284c73cc0b861906ce09e44ca1d Reviewed-on: https://gem5-review.googlesource.com/c/15256 Maintainer: Gabe Black <gabeblack@google.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
2019-01-22scons: add helpers to access GDB XML description filesCiro Santilli
Change-Id: Ic3b18887544b7710ed07a86d28dc62d8441b3476 Reviewed-on: https://gem5-review.googlesource.com/c/15255 Reviewed-by: Gabe Black <gabeblack@google.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Gabe Black <gabeblack@google.com>
2019-01-22scons: allow embedding arbitrary blobs into the gem5 executableCiro Santilli
The initial motivation for this is to embed the GDB XML target description files into the executable. Change-Id: I721e8dd37119d8e6eb376d7e9050b1094282bacc Reviewed-on: https://gem5-review.googlesource.com/c/15136 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com>
2019-01-22base: add support for GDB's XML architecture definitionCiro Santilli
This is done by implementing the Xfer:features:read packet of the GDB remote protocol. Before this commit, gem5 used the defaults of the GDB client. With this commit, gem5 can inform the client which registers it knows about. This allows in particular to support new registers which an older GDB client does not yet know about. The XML is not implemented in this commit for any arch, and falls back almost exactly to previous behaviour. The only change is that now gem5 replies to the Supported: request which the GDB clients sends at the beginning of the transaction with an empty feature list containing only the mandatory PacketSize= argument. Since the feature list does not contain qXfer:features:read, the GDB client knows that the gem5 server does support the XML format and uses its default registers as before. Change-Id: I5185f28b00e9b9cc8245f4b4262cc324c3d298c1 Reviewed-on: https://gem5-review.googlesource.com/c/15137 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2019-01-22arch-arm: Move AArch32 IMPLEMENTATION DEFINED registersGiacomo Travaglini
Moving AArch32 instruction accessing IMPLEMENTATION DEFINED registers from pseudo.[cc/hh] to misc.[cc/hh] in order to symmetrically match with AArch64 implementation. Change-Id: I27b0d65925d7965589b765269ae54129426e4c88 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/15735 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2019-01-22mem: Add tryTiming suppport to CommMonitorSascha Bischoff
The CommMonitor did not support tryTiming, which resulted in gem5 panicing if the CommMonitor was used. With this change, we update the CommMonitor pass through the tryTiming() calls. Change-Id: I86810170e5e10a0c5d63af76fc4a6ab70710d2fb Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/15736 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2019-01-22sim-se add readv and modifies writevBrandon Potter
Change-Id: I6cbce4389d5697da34058dc910306394e48c6582 Reviewed-on: https://gem5-review.googlesource.com/c/12117 Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com> Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>
2019-01-22sim-se: add ability to get/set sock metadataBrandon Potter
Add getsockopt, getsockname, setsockname, and getpeername system calls. Change-Id: Ifa1d9a95f15b4fb12859dbfd3c4bd248de2e3d32 Reviewed-on: https://gem5-review.googlesource.com/c/12116 Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com> Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>
2019-01-22sim-se: add syscalls related to pollingBrandon Potter
Fix poll so that it will use the syscall retry capability instead of causing a blocking call. Add the accept and wait4 system calls. Add polling to read to remove deadlocks that occur in the event queue that are caused by blocking system calls. Modify the write system call to return an error number in case of error. Change-Id: I0b4091a2e41e4187ebf69d63e0088f988f37d5da Reviewed-on: https://gem5-review.googlesource.com/c/12115 Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com> Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>
2019-01-22sim-se: add calls for network transmissionsBrandon Potter
Add recvfrom, sendto, recvmsg, and sendmsg system calls. Change-Id: I2eb50ea7823c8af57d99b3b8d443d2099418c06c Reviewed-on: https://gem5-review.googlesource.com/c/12114 Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com> Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>
2019-01-22sim-se: add socket-based functionalityBrandon Potter
Add socket, socketpair, bind, list, connect and shutdown system calls. Change-Id: I635af3fca410f96fe28f8fe497e3d457a9dbc470 Reviewed-on: https://gem5-review.googlesource.com/c/12113 Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com> Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>
2019-01-18base: Fix unitialized storageDaniel R. Carvalho
The bitunion is not being initialized on constructor to avoid performance overhead, and that generated a maybe-unitialized error when a sub-class was being copied before assigned in serialize's parseParam() in some compilers. This patch adds zero-initialization to the problematic variable to appease the compiler. Change-Id: I90fa6aa356b3e14ec25e3294b17ed10f429a9a38 Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br> Reviewed-on: https://gem5-review.googlesource.com/c/15635 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com>
2019-01-17tests: Fix tests/main.py so it can be run from anywhere.Gabe Black
tests/main.py was trying to find paths relative to itself using the string __name__ (which was __main__) when it should have been using the string __file__ which holds the name of the file being executed. Change-Id: I5ff4c42fc7d8b75ff6b96c3cde61baf731d84738 Reviewed-on: https://gem5-review.googlesource.com/c/15675 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2019-01-17mem: Allow inserts in the begining of a packet queueNikos Nikoleris
A packet queue keeps track of packets that are scheduled to be sent at a specified time. Packets are sorted such that the packet with the earliest scheduled time is at the front of the list (unless there are other ordering requirements). Previouly, the implemented algorithm didn't allow packets to be placed at the front of the queue resulting in uneccessary delays. This change fixes the implementation of schedSendTiming. Change-Id: Ic74abec7c3f4c12dbf67b5ab26a8d4232e18e19e Signed-off-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/15556 Reviewed-by: Bradley Wang <radwang@ucdavis.edu> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2019-01-17mem: Determine if a packet queue forces ordering at constructionNikos Nikoleris
A packet queue is typically used to hold on to packets that are schedules to be sent in the future or when they need to queue behind younger packets that have been sent out yet. Due to memory order requirements, some MemObjects need to maintain the order for packet (mostly responses) that reference the same cache block. Prior to this patch the ordering requirements where determined when the packet was scheduled to be sent. This patch moves the parameter to the constructor. Change-Id: Ieb4d94e86bc7514f5036b313ec23ea47dd653164 Signed-off-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/15555 Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2019-01-17cpu-o3: Make the smtCommitPolicy a Param.ScopedEnumNikos Nikoleris
The smtCommitPolicy is a parameter in the o3 cpu that can have 3 different values. Previously this setting was done through a string and a parser function would turn it into a c++ enum value. This changeset turns the string into a python Param.ScopedEnum. Change-Id: I3625f2c08a1ae0c3b0dce7a641c6ae1ce3fd79a5 Signed-off-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/15400 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2019-01-17cpu-o3: Make the smtROBPolicy a Param.ScopedEnumNikos Nikoleris
The smtROBPolicy is a parameter in the o3 cpu that can have 3 different values. Previously this setting was done through a string and a parser function would turn it into a c++ enum value. This changeset turns the string into a python Param.ScopedEnum. Change-Id: Ie104d055dbbc6e44997ae0c1470de714239be5a3 Signed-off-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/15399 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2019-01-17cpu-o3: Make the smtIQPolicy a Param.ScopedEnumNikos Nikoleris
The smtIQPolicy is a parameter in the o3 cpu that can have 3 different values. Previously this setting was done through a string and a parser function would turn it into a c++ enum value. This changeset turns the string into a python Param.ScopedEnum. Change-Id: Ieecf0a19427dd250b0d5ae3d531ab46a37326ae5 Signed-off-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/15398 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2019-01-17cpu-o3: Make the smtLSQPolicy a Param.ScopedEnumNikos Nikoleris
The smtLSQPolicy is a parameter in the o3 cpu that can have 3 different values. Previously this setting was done through a string and a parser function would turn it into a c++ enum value. This changeset turns the string into a python Param.ScopedEnum. Change-Id: I82041b88bd914c5dc660058d9e3998e3114e7c35 Signed-off-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/15397 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2019-01-17cpu-o3: Make the smtFetchPolicy a Param.ScopedEnumNikos Nikoleris
The smtFetchPolicy is a parameter in the o3 cpu that can have 5 different values. Previously this setting was done through a string and a parser function would turn it into a c++ enum value. This changeset turns the string into a python Param.ScopedEnum. Change-Id: Iafb4b4b27587541185ea912e5ed581bce09695f5 Signed-off-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/15396 Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com> Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>
2019-01-17python: Add support for scoped enumsNikos Nikoleris
At the moment gem5 has support for enum params that either generate a unscoped within the Enums namespace or a struct encapsulated enum. The Enums namespace is getting quite big and some params have the same names which results in collisions. This change adds support for the scoped enums. Change-Id: I930e1cc3b814081627b653939e75d6c43956a334 Signed-off-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/15395 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2019-01-16cpu: dev: sim: gpu-compute: Banish some ISA specific register types.Gabe Black
These types are IntReg, FloatReg, FloatRegBits, and MiscReg. There are some remaining types, specifically the vector registers and the CCReg. I'm less familiar with these new types of registers, and so will look at getting rid of them at some later time. Change-Id: Ide8f76b15c531286f61427330053b44074b8ac9b Reviewed-on: https://gem5-review.googlesource.com/c/13624 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com>
2019-01-16arch: Make the ISA register types aliases for the global types.Gabe Black
The ISA specific types can thus be phased out. Change-Id: I8ea531a099fad140a4ec9c91cd972fe044111d60 Reviewed-on: https://gem5-review.googlesource.com/c/13623 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2019-01-16arm: Make the fp register types 64 bits.Gabe Black
This matches the other ISAs. Change-Id: I84de91efde2529f4aecc7b26b84266d97459738c Reviewed-on: https://gem5-review.googlesource.com/c/13622 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
2019-01-16mem-cache: Access Map Pattern Matching PrefetcherJavier Bueno
Implementation of the Access Map Pattern Matching prefetcher Based in the description of the following paper: Access map pattern matching for high performance data cache prefetch. Ishii, Y., Inaba, M., & Hiraki, K. (2011). Journal of Instruction-Level Parallelism, 13, 1-24. Change-Id: I0d4b7f7afc2ab4938bdd8755bfed26e26a28530c Reviewed-on: https://gem5-review.googlesource.com/c/15096 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2019-01-16mem-cache: Signature Path PrefetcherJavier Bueno
Related paper: Lookahead Prefetching with Signature Path J Kim, PV Gratz, ALN Reddy The 2nd Data Prefetching Championship (DPC2), 2015 Change-Id: I2319be2fa409f955f65e1bf1e1bb2d6d9a4fea11 Reviewed-on: https://gem5-review.googlesource.com/c/14737 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2019-01-16mem-cache: allow prefetchers to emit page crossing referencesJavier Bueno
QueuedPrefetcher takes the responsability to check for page crossing references. Change-Id: I0ae6bf8be465118990d9ea1cac0da8f70e69aeb1 Reviewed-on: https://gem5-review.googlesource.com/c/14735 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2019-01-16mem-cache: virtual address support for prefetchersJavier Bueno
Prefetchers can be configured to operate with virtual or physical addreses. The option can be configured through the "use_virtual_addresses" parameter of the Prefetcher object. Change-Id: I4f8c3687988afecc8a91c3c5b2d44cc0580f72aa Reviewed-on: https://gem5-review.googlesource.com/c/14416 Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
2019-01-16arch-arm: Read VMPIDR instead of MPIDR when EL2 is EnabledGiacomo Travaglini
Trying to read MPIDR(_EL1) from EL1, should return the value of VMPIDR_EL2 if EL2 is enabled. This patch is modifying the utility function for reading MPIDR in order to match this behaviour for both AArch32 and AArch64. Change-Id: I32c2d4d5052f509e6e0542a5314844164221c6a3 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/15617 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2019-01-16arch-arm: Added TLBI_ALL EL2 instructionAnouk Van Laer
This patch is adding TLBI_ALLE2(IS) operations to the arm ISA. Change-Id: I8e35cff9a2cc414f4c5fbbc5aa0cfe5023a3f011 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Anouk Van Laer <anouk.vanlaer@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/15616 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2019-01-16arch-riscv: Add interrupt handlingAlec Roelke
Implement the Interrupts SimObject for RISC-V. This basically just handles setting and getting the values of the interrupt-pending and interrupt-enable CSRs according to the privileged ISA reference chapter 3.1.14. Note that it does NOT implement the PLIC as defined in chapter 7, as that is used for handling external interrupts which are defined based on peripherals that are available. Change-Id: Ia1321430f870ff5a3950217266fde0511332485b Reviewed-on: https://gem5-review.googlesource.com/c/14377 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2019-01-16arch-riscv: Fix reset function and styleAlec Roelke
In addition to fixing some style issues with resetting, this patch fixes what happens on reset. The RISC-V privileged ISA reference manual says that, on reset: 1. Privilege mode is set to M 2. mstatus.mie <- 0; mstatus.mprv <- 0 3. PC <- reset vector 4. mcause <- reset cause (0 if there is no distinguishing causes) 5. Everything else is undefined Because of 5, everything else will be left alone Change-Id: I81bdf7a88b08874e3c3d5fc6c7f3ca2d796496b8 Reviewed-on: https://gem5-review.googlesource.com/c/14376 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2019-01-15cpu: Fix usage of setArchVecElemGiacomo Travaglini
setArchVecElem should create a VecElemClass RegId, and not a VecRegClass. Initializing a VecRegClass with three arguments makes it panic Change-Id: I6c398d67305bfe7bea12cb02edd4f4c3a202e69a Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Giacomo Gabrielli <giacomo.gabrielli@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/15655 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2019-01-15arch-arm: Fix usage of RegId constructor for VecElemGiacomo Travaglini
RegId() constructor requires three arguments in case of a VecElem register: the class, the vector index and the element index inside the vector, otherwise it panics. Change-Id: Ic842df4dcddaffa83b211aa6e1dd1953cafa4951 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Giacomo Gabrielli <giacomo.gabrielli@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/15615 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2019-01-14arm: Stop using the FloatReg and FloatRegBits types.Gabe Black
This will let us make those types 64 bits to be in line with the other architectures. Change-Id: I5aef5199f4d2d5bb1558afedac5c6c92bf95c021 Reviewed-on: https://gem5-review.googlesource.com/c/13621 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
2019-01-14config: De-nest the code in Port.splice().Gabe Black
The error checking in that function used an if/else structure where one of the two branches would be the error condition which would cause the function to exit. Because the function would exit if an error was detected, there's no reason to have the non-error condition guarded in the other half of the if. This change de-nests the non-error cases to make the function simpler and easier to read. Change-Id: Idedf54e84a178fa5a2a47f96373374152e420cf3 Reviewed-on: https://gem5-review.googlesource.com/c/15516 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
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