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AgeCommit message (Expand)Author
2020-01-13systemc: keep SC_CONCAT* macroEarl Ou
2020-01-11arch: Make the generic micropc enabled PCState set nupc to 1.Gabe Black
2020-01-10dev-arm: VExpress_GEM5_Base, fix daughterboard referenceAdrian Herrera
2020-01-09tests,base: Added GTest for base/socket.ccBobby R. Bruce
2020-01-09tests: Updated gtest/logging.cc to print log rather than fail.Bobby R. Bruce
2020-01-09base: Include some required headers in amo.hh.Gabe Black
2020-01-09base, gpu-compute: Move gpu AMOs into the generic headerGiacomo Travaglini
2020-01-08tests: Added functionality to allow the ignoring of test suitesBobby R. Bruce
2020-01-08arch, base: Move arm AtomicOpFunctor into the generic headerGiacomo Travaglini
2020-01-08base: Move AtomicOpFunctors to a dedicated headerGiacomo Travaglini
2020-01-08scons: Add '-Wl,--as-needed' to default LINKFLAGSYu-hsin Wang
2020-01-07arch,sim: Promote the m5ops_base param to the System base class.Gabe Black
2020-01-07cpu: Disable O3CPU value forwarding with write strobesGabor Dozsa
2020-01-07cpu: Use enums for O3CPU store value forwardingGabor Dozsa
2020-01-07system-arm: GICv2/GICv3 have different Distributor addressesGiacomo Travaglini
2020-01-07system-arm: Rename ARM bootloader sourceGiacomo Travaglini
2020-01-07system-arm: Rename ARM bootloader directoriesGiacomo Travaglini
2020-01-07misc: Reflect changes of arm bootloader nameAdrian Herrera
2020-01-07scons: Cleanup code that enables asan and ubsanNikos Nikoleris
2020-01-07mem-cache: Forward snoops when the cache is not respondingNikos Nikoleris
2020-01-07mem-cache: Ensure that responses get data from the right sourceNikos Nikoleris
2020-01-07systemc: fix gem5_to_tlm bridgeEarl Ou
2020-01-07fastmodel: Implement the vecPredReg accessor functions.Gabe Black
2020-01-07arch,sim: Stop decoding the pseudo inst subfunc value.Gabe Black
2020-01-06arch,sim: Use the guest ABI mechanism with pseudo instructions.Gabe Black
2020-01-06arch-arm: Semihosting, specify files root dirAdrian Herrera
2020-01-06dev-arm: Fix SMMUv3 walkMasks in page table opsMichiel van Tol
2020-01-06dev-arm: Fix SMMUv3 16KB next-level table address maskingGiacomo Travaglini
2020-01-06dev-arm: GICv3, handle GICR_ICFGR0 WI behaviourAdrian Herrera
2020-01-06mem-cache: Avoid write merging if there are reads in betweenNikos Nikoleris
2020-01-06configs-arm: enable PMU instantiation in CpuClusterAdrian Herrera
2020-01-03sim: Move destructor of Port to publicYu-hsin Wang
2020-01-03cpu: Fix issue with MinorCPU predicated-false mem. accessesGiacomo Gabrielli
2020-01-03cpu: Disable MinorCPU value forwarding with write strobesGabor Dozsa
2020-01-03misc: Added 'fastmodel' to MAINTAINERSBobby R. Bruce
2019-12-30fastmodel: Fix compilation errorsChun-Chen TK Hsu
2019-12-27fastmodel: Move ARM but not CortexA76 specific bits to the IRIS TC.Gabe Black
2019-12-27fastmodel: Move the ARM IRIS threadcontext into CortexA76.Gabe Black
2019-12-27fastmodel: Mostly collapse ARM base classes for the CortexA76 CPU.Gabe Black
2019-12-27fastmodel: Checkpoint the TCs when checkpointing a fast model CPU.Gabe Black
2019-12-27fastmodel: Handle "special" vector regs without calling into IRIS.Gabe Black
2019-12-24fastmodel: Implement readVecRegFlat for ArmThreadContext.Gabe Black
2019-12-24fastmodel: Determine what space to use for breakpoints dynamically.Gabe Black
2019-12-23fastmodel: Implement PC based events.Gabe Black
2019-12-23tests: Always print stderr in gem5 FixturesGiacomo Travaglini
2019-12-21base: Fix negative op-assign of SatCounterDaniel R. Carvalho
2019-12-20configs: arm realview(64) regressions using VExpress_GEM5_V1Giacomo Travaglini
2019-12-20systemc: Fix tlm2 socket integrationJui-min Lee
2019-12-20arch-arm: Fix clang warningsJui-min Lee
2019-12-19arch-arm: Fix decoding of LDFF1x scalar plus scalarAdrià Armejach
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