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AgeCommit message (Expand)Author
2019-05-30arch, base, sim: Replace Copy(String)?(In|Out) with equivalent code.Gabe Black
2019-05-29sim-se: const for loader's loadSection paramBrandon Potter
2019-05-29cpu: Added correct return type for ROB::countInstsAndrea Mondelli
2019-05-29mem-cache: Accuracy-based rate control for prefetchersJavier Bueno
2019-05-29sim-se: add a release parameter to Process.pyCiro Santilli
2019-05-29mem-cache: Support for page crossing prefetchesJavier Bueno
2019-05-29mem: Add a readString method to the PortProxy which takes a char *.Gabe Black
2019-05-29mem: Use a const T & in write<> to avoid an unnecessary copy.Gabe Black
2019-05-29arch, base, dev, sim: Remove now unnecessary casts from PortProxy methods.Gabe Black
2019-05-29mem, arm: Replace the pointer type in PortProxy with void *.Gabe Black
2019-05-29mem, arm: Move some helper methods into the base PortProxy class.Gabe Black
2019-05-29arm, mem: Move the SecurePortProxy subclass into it's own file.Gabe Black
2019-05-28mem: Parameterize coherent xbar sanity checksTiago Muck
2019-05-28mem: Snoop filter support for large systemsTiago Muck
2019-05-28base: Add warn_if_once macroTiago Muck
2019-05-28cpu: Remove assert causing issues with x86 Linux bootGiacomo Gabrielli
2019-05-24arch-arm: Fix fallthrough when trapping at EL2Giacomo Travaglini
2019-05-23arch-arm: Trap virtual accesses to GICv3 SGI registersGiacomo Travaglini
2019-05-23arch-arm: Expose haveGicv3CPUInterface to the ISA interfaceGiacomo Travaglini
2019-05-23arch-arm: Change mcrMrc15TrapToHyp signatureGiacomo Travaglini
2019-05-22mem: Add invalid context id check on LLSC checksTiago Muck
2019-05-22sim-se: remove comment for code that movedBrandon Potter
2019-05-22dev-arm: Provide a GICv3 ITS ImplementationGiacomo Travaglini
2019-05-21sim-se: change syscall function signatureBrandon Potter
2019-05-21sim-se: remove /sys from special pathsTony Gutierrez
2019-05-21scons: Move the marshal binary to the build directoryChun-Chen TK Hsu
2019-05-20misc: Added dot_writer for Ruby's network topologyTiago Muck
2019-05-20mem-cache: Add multi-prefetcher adaptorAndreas Sandberg
2019-05-20sim: Make the Process create function use the object loader mechanism.Gabe Black
2019-05-20x86: Add an object file loader for linux.Gabe Black
2019-05-20sparc: Add an object file loader for linux and solaris.Gabe Black
2019-05-20riscv: Add an object file loader for linux.Gabe Black
2019-05-20power: Add an object file loader for linux.Gabe Black
2019-05-20mips: Add an object file loader for linux.Gabe Black
2019-05-18arm: Add an object file loader for linux and freebsd.Gabe Black
2019-05-18alpha: Add an object file loader for linux.Gabe Black
2019-05-18base: Add a type for keeping track of object file loaders.Gabe Black
2019-05-18arch, base, cpu, dev, mem, sim: Remove #if 0-ed out code.Gabe Black
2019-05-17configs: Generalize FileSystemConfig for non se.pyJason Lowe-Power
2019-05-17arch-arm: implement VMINNM and VMAXNM scalar versionCiro Santilli
2019-05-17arch-arm: implement VMINNM and VMAXNM SIMD versionCiro Santilli
2019-05-17arch-arm: rename operands to match spec in isa/formats/fp.isaCiro Santilli
2019-05-14mem-ruby: MOESI_CMP_dir cleanupTiago Muck
2019-05-14mem-ruby: Cache latencies for MOESI_CMP_dirTiago Muck
2019-05-14mem-ruby: Hit latencies defined by the controllersTiago Muck
2019-05-14mem-ruby: Do not change blocked msg enqueue infoTiago Muck
2019-05-14mem-ruby: Unique ranks for MOESI_CMP_dir in portsTiago Muck
2019-05-14mem-ruby: Change MOESI_CMP_Dir L2 addressingTiago Muck
2019-05-14mem-ruby: Fix MOESI_CMP_dir debug msgTiago Muck
2019-05-14mem-ruby: Prevent response stalls on MOESI_CMP_directoryTiago Muck
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