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2019-12-27fastmodel: Handle "special" vector regs without calling into IRIS.Gabe Black
These registers don't have an architectural equivalent, but they may need to be accessed by generic code, for instance the code that checkpoints a thread context. Change-Id: I4a18f44f2c09e379a4629c8e3eb8070b5c01918e Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23784 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-12-24fastmodel: Implement readVecRegFlat for ArmThreadContext.Gabe Black
This just calls readVecReg after constructing a RegId. Change-Id: Ia26b9bb874fec62f98bd5e4d3c6aa1059766c2f6 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23783 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
2019-12-24fastmodel: Determine what space to use for breakpoints dynamically.Gabe Black
This was hardcoded as 5, but should be determined based on the memory space IDs the fast model returns. What we do now is have a specific override for ARM (perhaps conceptually the A76) which looks for an address space called "Current" which seems to work well. It's possible that the appropriate address space for a different model might have a different number, or even a different name. This may need to be further specialized/parameterized in those cases. Change-Id: Ie1ef99675fd9bccab50b7fc7add16b82a93bd60b Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22143 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-12-23fastmodel: Implement PC based events.Gabe Black
These use the IRIS breakpoint API to stop the models at the appropriate points. There seems to be a slightly wonky interaction between breakpoints and stepping, where if you stop at a breakpoint and then step, you might end up moving forward more than the number of requested instructions. Change-Id: I31f13a120cfc1ad2ec3669ee8befd6d21b328bb2 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22122 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-12-23tests: Always print stderr in gem5 FixturesGiacomo Travaglini
At the moment is impossible when observing an upstream kokoro failure to understand what went wrong. This is because the only thing that gets printed is the exception traceback and the command line generating it. Most of the time it will be something like Traceback (most recent call last): File "/tmpfs/src/git/jenkins-gem5-prod/tests/../ext/testlib/runner.py", line 195, in setup fixture.setup(testitem) File "/tmpfs/src/git/jenkins-gem5-prod/tests/gem5/fixture.py", line 115, in setup self._setup(testitem) File "/tmpfs/src/git/jenkins-gem5-prod/tests/gem5/fixture.py", line 160, in _setup log_call(log.test_log, command) File "/tmpfs/src/git/jenkins-gem5-prod/tests/../ext/testlib/helper.py", line 103, in log_call raise subprocess.CalledProcessError(retval, cmdstr) With this patch we dump the stderr so that the fail reason is exposed to the viewer. Change-Id: Ic3d0fe75ec4d0543d95e9624dc5287afb4af3b8b Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23843 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2019-12-21base: Fix negative op-assign of SatCounterDaniel R. Carvalho
The value of the add and subtract assignment operations can be negative, and this was not being handled properly previously. Regarding shift assignment, the standard says it is undefined behaviour if a negative number is given, so add assertions for these cases. Change-Id: I2f1e4143c6385caa80fb25f84ca8edb0ca7e62b7 Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23664 Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-12-20configs: arm realview(64) regressions using VExpress_GEM5_V1Giacomo Travaglini
This patch is updating the arm regression configs so that the newer VExpress_GEM_V1 platform is used instead of the older VExpress_EMM and VExpress_EMM64. A new optional kernel_mode argument has been added in order to distinguish between realview and realview64 platforms. If not provided the config will assume the machine is running a AArch64 kernel. Other notable additions: - DTB autogeneration in regressions - Using minimal m5exit.squashfs disk image Change-Id: Ia230565f072fe3eb7756c41876dba4657583f4df Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22687 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
2019-12-20systemc: Fix tlm2 socket integrationJui-min Lee
This change will make the systemc extension in gem5 more compatible to the reference implementation by Accellera. * Remove the alias of sc_port's bind in initiator socket. * Ignore -Woverloaded-virtual in initiator socket. Change-Id: I229e4d493e01d26174c5662ad71d4859d546d307 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23864 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com>
2019-12-20arch-arm: Fix clang warningsJui-min Lee
Fix some warnings reported by clang. * missing override in {freebsd,linux}/process.hh Change-Id: I67c36a0785ac90614211d640fd58d3ffe187c17e Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23863 Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br> Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-12-19arch-arm: Fix decoding of LDFF1x scalar plus scalarAdrià Armejach
First-faulting loads do allow Rm == 0x1f. Change-Id: Ib9bcb55e126653813fdbb7c29970af23a2471ebb Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23803 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-12-18arch-arm: Semihosting, fix SYS_FLENAdrian Herrera
SYS_FLEN was incorrectly handled as SYS_ISTTY. This patch fixes this behaviour. Change-Id: I66e0b97d8b44d2cb78e0b1bb940fd6f4b52c658f Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23752 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-12-18sim: kernelExtras optional load addressesAdrian Herrera
This patch provides a new "System" parameter named "kernel_extras_addrs". This allows to optionally specify fixed load addresses for the additional kernel objects. This is useful to load arbitrary blobs into memory. Change-Id: I4725763b86c29f72282d1c184d4284d90f9d3016 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23566 Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-12-18python: fix "fatal" usage in fdthelperAdrian Herrera
"fatal" was not correctly imported in the fdthelper module, which caused a crash when reporting errors. Change-Id: I7ee9dcde1f0288e11e56dba67ead4aa2d6d67e02 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23753 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-12-18arch-arm: Secure EL2 checkingAdrian Herrera
This patch adds Armv8.4-SecEL2 checking. Helpers implementing EL2Enabled, IsSecureEL2Enabled and HaveSecureEL2Ext following the architecture pseudocode are provided. These are intended to be used for checking register access permissions. Change-Id: I3d06d0127cf165c1eeaf3302830742d610cef719 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23766 Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-12-18arch-arm: AArch64 trap check, arbitrary ECs/ImmsAdrian Herrera
This patch generalises trap checking when accessing system registers in AArch64. Depending on the accessed register, a different Exception Class (EC) and immediate value may be set. Previously this only took SIMD traps into account. Change-Id: I30717676a210c770531e39e4c6a6e1fbfdfdc583 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23765 Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-12-18x86: Fix some bugs with KVM in SE mode on Intel machines.Gabe Black
The granularity bit should be set since the segment limit should be interpreted as a number of pages, not bytes. A comment indicates that NX support is enabled, but the bit wasn't being set. That's now set to be consistent with FS mode. The SVME bit is now turned off, since Intel CPUs don't have SVME, and enabling it apparently makes them upset. Also disable CR4 bits which enable features neither gem5 nor apparently my workstation support. Change-Id: I72d5a07871dede8763b0dd188a52fe5eb6bde6ea Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23361 Reviewed-by: Ayaz Akram <yazakram@ucdavis.edu> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-12-17sim: Include some required headers in the syscall debug macros header.Gabe Black
Everything that includes syscall_debug_macros.hh and uses the macro in it will need these headers, so they should be included through syscall_debug_macros.hh. The consumer shouldn't have to know what the macros use internally and to include extra headers to support them. Change-Id: I9bfa932368daec0772d552357ecad8790b4cfead Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23459 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2019-12-17fastmodel: Tell fast model not to shutdown when time stops.Gabe Black
Change-Id: I000e7809a2c8850eb31e5615caf1d88b537fea8d Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22121 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Chun-Chen TK Hsu <chunchenhsu@google.com> Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-12-17fastmodel: Implement port proxies.Gabe Black
This plumbing is simple and largely copied from other implementations within gem5. This mechanism should be refactored so that the duplication is unnecessary. Change-Id: Ibcdf759b7fba1d574e8e2ba04249afdd92c6560c Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22120 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Chun-Chen TK Hsu <chunchenhsu@google.com> Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-12-17fastmodel: Create a TLB model which uses IRIS to do translations.Gabe Black
Change-Id: I806dc8cdacce57e6ec31d2421b9e6b9733c7da02 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22119 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
2019-12-17fastmodel: Add an address translation mechanism to the ThreadContext.Gabe Black
This will be used by the TLB to do the actual translation. Unfortunately there isn't a great way to tell what translation type to use, so we just go through all of them for now. The ARM subclass might specialize and figure out which address spaces to use based on control register state. Change-Id: Id1fcad66554acf9d69af683917b3c2834f825da0 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22118 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-12-17misc: Add Giacomo Travaglini to PMCJason Lowe-Power
Change-Id: I025a4bcde558187d02a7e13c6d644555f7148676 Signed-off-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23723 Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu> Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu> Tested-by: kokoro <noreply+kokoro@google.com>
2019-12-17base: Fix AddrRange::isSubset() checkNikos Nikoleris
Making _end non-inclusive, introduced a bug in isSubset() which was checking if _end is included in the input address range. This CL changes the behavior and now we test if _end - 1 is in the range. Change-Id: Ib8822472b7c266e10d55f3d5cf22a46aa45c1fc7 Signed-off-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23663 Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu> Tested-by: kokoro <noreply+kokoro@google.com>
2019-12-17tests: Setup Kokoro to run the GTest suite.Bobby R. Bruce
Change-Id: If700eed24b2902d04a9b0ee72b72e9e6a3472ef5 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23724 Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-12-17scons: Added channel_addr.cc dependency to channel_addr GTestBobby R. Bruce
In some circumstances not including channel_addr.cc as a dependency for the channel_addr.test compilation resulted in a build failure (this was observed in gem5's Kokoro CI system). This commit fixes this problem. Change-Id: Ic38a104a1e6bf655fc64158b556e6227d5ac3981 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23603 Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-12-17fastmodel: Add a header for IRIS MSN constants.Gabe Black
Change-Id: I06a7d7db95ec1ce65945c9e09f812f0b69aaa8e6 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23643 Reviewed-by: Gabe Black <gabeblack@google.com> Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Gabe Black <gabeblack@google.com> Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-12-17config: Default the indirect branch predictor to "None".Gabe Black
Other scripts (like se.py) blindly try to apply the indirect predictor if one is set. Because this option defaults to something, there's no way (as far as I know) to purposefully select nothing, and so the simulator crashes. Users shouldn't have to proactively prevent gem5 from killing itself regardless, so the default was changed to "None". Change-Id: Ic3382b8065442d6705b1c6a656646598d9d5c322 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23360 Reviewed-by: Ciro Santilli <ciro.santilli@arm.com> Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-12-16sim: kernelExtras if no kernel providedAdrian Herrera
kernelExtras facilitates a way for users to provide additional blobs to load into memory. As of now, the creation of the extra images is done independently of the kernel being provided, but the loading is only done if the kernel is present. This patch refactors the loading of extra images to be committed if no kernel is present. Change-Id: I900542e1034ade8d757d01823cfd4a30f0b36734 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22850 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Gabe Black <gabeblack@google.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2019-12-13dev-virtio,configs: expose 9p diod virtio on ARMCiro Santilli
9p allows the guest Linux kernel to mount a host directory into the guest. This allows to very easily modify test programs after a run at the end of boot, without the need to re-insert the changes into a disk image. It is enabled on both fs.py and fs_bigLITTLE.py with the --vio-9p option. Adapted from code originally present on the wiki: http://gem5.org/WA-gem5 As documented in the CLI option help, the current setup requires the guest to know the full path to the host share, which is annoying, but overcoming that would require actually parsing a bit of the protocol rather than just forwarding everything to diod. Change-Id: Iaeb1ed185dccfa8332fe6657a54e7550f64230eb Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22831 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-12-13dev-virtio: VIO9P turns on diod verbose output with -d 1Ciro Santilli
Change-Id: I97e5762f4aca384068b87e22902e071fa3014ceb Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22829 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu> Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
2019-12-13dev-virtio: don't set the 9p default rootCiro Santilli
It is better to force users to explicitly set this argument, since it is unlikely that we will find one safe option for all users. Change-Id: I612520a44efd205a029a40cd13402584d16e1d88 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22828 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2019-12-13dev-virtio: use diod basename as the default 9p pathCiro Santilli
This allows diod to be present anywhere in the PATH by default, which works because we are already using execlp. Change-Id: I9d0b6c9a75f32cf0cb5d8f52bb00c465e4d43e1b Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22827 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2019-12-12mem: Encapsulate mapping gem5 to host address spaceDaniel R. Carvalho
Create a function to encapsulate mapping an address in gem5's address space to the host's address space. The returned value can be used to access the contents of the given address. As a side effect, make the local variable hostAddr use snake_case to comply with gem5's coding style. Change-Id: I2445d3ab4c7ce5746182b307c26cbafc68aa139c Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22610 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-12-12mem-cache: Move unused prefetches counter updateDaniel R. Carvalho
The number of unused prefetches should be updated every time a block is invalidated, therefore we move the update to within the corresponding function. Change-Id: If3ac2ea43611525bd3c36d628d88382042fcb7dc Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18908 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2019-12-12python: Convert terminal escape sequences to strings.Gabe Black
In python 3, the curses escape sequences are bytes objects and not strings, making them unsuitable to concatenate to strings which are being print()-ed. This uses the decode() method to turn them from bytes objects into string objects, assuming they represent UTF-8. In python 2, bytes objects and strings are treated interchangeably, and so this isn't necessary. Change-Id: Ifc5d788e1c62751090a350d3a064e89f434559e8 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23265 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-12-11arch-arm: Always initialize SVE memDataGiacomo Travaglini
Some compilers will produce a warning when using an uninitialized memData. JIRA: https://gem5.atlassian.net/browse/GEM5-196 Change-Id: I19e197b15729a03da546a0188917a9b3e7bf31b7 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23525 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-12-11arch-arm: Avoid creating an empty byteEnable vectorGiacomo Travaglini
This behaviour will be forbidden in following patches. Instead, create an all true vector. JIRA: https://gem5.atlassian.net/browse/GEM5-196 Change-Id: I61d2852610281f2d7c7a669dcb4d2728be194f52 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23524 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-12-11cpu: Replace empty byteEnable check with Request::isMaskedGiacomo Travaglini
This should be the interface to be used to check if the request has some masked bytes. JIRA: https://gem5.atlassian.net/browse/GEM5-196 Change-Id: I1ab5fd266c7b63a928aada32ae6d4f7fa915f2b6 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23523 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-12-11cpu: Fix coding style (byteEnable->byte_enable)Giacomo Travaglini
Change-Id: I2206559c6c2a6e6a0452e9c7d9964792afa9f358 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23282 Maintainer: Jason Lowe-Power <jason@lowepower.com> Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
2019-12-11cpu: Add byteEnable assertions to readMem and initateMemReadGiacomo Travaglini
Those are already present in writeMem; looking for consistency Change-Id: Ib85e0db228bc73e3ac64155d1290444cf6864a8c Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23281 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br> Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu> Tested-by: kokoro <noreply+kokoro@google.com> Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
2019-12-10sim,arch: Collapse the ISA specific versions of m5Syscall.Gabe Black
The x86 version doesn't do anything x86 specific, and so can be used generically in sim/pseudo_inst.(hh|cc) Jira Issue: https://gem5.atlassian.net/browse/GEM5-187 Change-Id: I46c2a7d326bd7a95daa8611888051c180e92e446 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23177 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com>
2019-12-10arch,cpu,sim: Push syscall number determination up to processes.Gabe Black
The logic that determines which syscall to call was built into the implementation of faults/exceptions or even into the instruction decoder, but that logic can depend on what OS is being used, and sometimes even what version, for example 32bit vs. 64bit. This change pushes that logic up into the Process objects since those already handle a lot of the aspects of emulating the guest OS. Instead, the ISA or fault implementations just notify the rest of the system that a nebulous syscall has happened, and that gets propogated upward until the process does something with it. That's very analogous to how a system call would work on a real machine. When a system call happens, the low level component which detects that should call tc->syscall(&fault), where tc is the relevant thread (or execution) context, and fault is a Fault which can ultimately be set by the system call implementation. The TC implementor (probably a CPU) will then have a chance to do whatever it needs to to handle a system call. Currently only O3 does anything special here. That implementor will end up calling the Process's syscall() method. Once in Process::syscall, the process object will use it's contextual knowledge to determine what system call is being requested. It then calls Process::doSyscall with the right syscall number, where doSyscall centralizes the common mechanism for actually retrieving and calling into the system call implementation. Jira Issue: https://gem5.atlassian.net/browse/GEM5-187 Change-Id: I937ec1ef0576142c2a182ff33ca508d77ad0e7a1 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23176 Maintainer: Gabe Black <gabeblack@google.com> Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Brandon Potter <Brandon.Potter@amd.com>
2019-12-10x86: Stop manually clearing RFLAGS.RF after a system call.Gabe Black
The system call stub KVM uses in SE mode to call the system call pseudo instruction which ultimately calls m5Syscall already uses sysret, and the implementation of sysret clears both the RF and VM bits itself. There's no reason to do that again explicitly here. Jira Issue: https://gem5.atlassian.net/browse/GEM5-187 Change-Id: Id7b5417564e3f3492ba6efb8ed36fab2f4c38e09 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23175 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com>
2019-12-10arch: Get rid of the now unused setSyscallArg.Gabe Black
Setting syscall args isn't really something we need to do in gem5, since that will be taken care of by the code actually calling the syscall. We just need to be able to retrieve the value it put there. Jira Issue: https://gem5.atlassian.net/browse/GEM5-187 Change-Id: I0bb6d5d0207a7892414a722b3788cb70ee509582 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23174 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com>
2019-12-10arch: Stop using setSyscallArg to set argc and argv.Gabe Black
In Alpha and MIPS, the argc and argv values should be in what happens to be the first and second syscall argument registers, but that's not by definition. The process objects of both those ISAs know what registers to use intrinsically, so there's also no reason to call out to a helper method which acts as a part of the Process's interface to the rest of gem5. Jira Issue: https://gem5.atlassian.net/browse/GEM5-187 Change-Id: Id8fa38ab1fc2ac6436e94ad41303439973fded10 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23173 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com>
2019-12-10sim: Add a wrapper/subclass for SyscallDesc which uses GuestABI.Gabe Black
This will let system call implementations take arguments naturally, and centrally defined, potentially complex, and ISA/context specific mechanisms will automatically gather the arguments and store any result. Jira Issue: https://gem5.atlassian.net/browse/GEM5-187 Change-Id: I68d265e0bab5de372ba975e4c7e9bb2d968c80af Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23172 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com>
2019-12-10sim: Add a mechanism to translate ABIs to call host funcs from a TC.Gabe Black
The guest ABI is specified as a template parameter. This makes it possible for host simcall handlers to be called through different ABIs which might be from different ISAs, or might be from different contexts within the same ISA (32 vs 64 bit, syscall vs. function vs. pseudo instrunction vs. semihosting call). Jira Issue: https://gem5.atlassian.net/browse/GEM5-187 Change-Id: I66a0f558e9c1f70a142b69b0dd95bd71e41d898b Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23171 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com>
2019-12-10sim: Get rid of the now unused SyscallDesc flags and methods.Gabe Black
Jira Issue: https://gem5.atlassian.net/browse/GEM5-187 Change-Id: Icee18a4bd77a346d7f82ef4988651b753392d51e Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23170 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com>
2019-12-10arch: Use ignoreWarnOnceFunc instead of the WarnOnce flag.Gabe Black
Jira Issue: https://gem5.atlassian.net/browse/GEM5-187 Change-Id: I9bbffcc74ec4f3df4effa5c50f0a4a688c5b6016 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23169 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com>
2019-12-10sim: Reintroduce the ignoreWarnOnceFunc syscall handler.Gabe Black
Instead of just using warn_once, we'll gate each warning on a bool which is associated with the syscall desc pointer. To avoid having to keep warn once bookkeeping in every syscall desc, we put it in a map which is looked up at runtime. Jira Issue: https://gem5.atlassian.net/browse/GEM5-187 Change-Id: I1dcce48de91b8a635f9f3df3bfc0ed6ba1291c4f Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23168 Maintainer: Gabe Black <gabeblack@google.com> Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Brandon Potter <Brandon.Potter@amd.com>
generated by cgit v1.2.3 (git 2.25.1) at 2025-02-26 23:17:23 +0000