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2019-12-17tests: Setup Kokoro to run the GTest suite.Bobby R. Bruce
Change-Id: If700eed24b2902d04a9b0ee72b72e9e6a3472ef5 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23724 Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-12-17scons: Added channel_addr.cc dependency to channel_addr GTestBobby R. Bruce
In some circumstances not including channel_addr.cc as a dependency for the channel_addr.test compilation resulted in a build failure (this was observed in gem5's Kokoro CI system). This commit fixes this problem. Change-Id: Ic38a104a1e6bf655fc64158b556e6227d5ac3981 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23603 Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-12-17fastmodel: Add a header for IRIS MSN constants.Gabe Black
Change-Id: I06a7d7db95ec1ce65945c9e09f812f0b69aaa8e6 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23643 Reviewed-by: Gabe Black <gabeblack@google.com> Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Gabe Black <gabeblack@google.com> Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-12-17config: Default the indirect branch predictor to "None".Gabe Black
Other scripts (like se.py) blindly try to apply the indirect predictor if one is set. Because this option defaults to something, there's no way (as far as I know) to purposefully select nothing, and so the simulator crashes. Users shouldn't have to proactively prevent gem5 from killing itself regardless, so the default was changed to "None". Change-Id: Ic3382b8065442d6705b1c6a656646598d9d5c322 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23360 Reviewed-by: Ciro Santilli <ciro.santilli@arm.com> Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-12-16sim: kernelExtras if no kernel providedAdrian Herrera
kernelExtras facilitates a way for users to provide additional blobs to load into memory. As of now, the creation of the extra images is done independently of the kernel being provided, but the loading is only done if the kernel is present. This patch refactors the loading of extra images to be committed if no kernel is present. Change-Id: I900542e1034ade8d757d01823cfd4a30f0b36734 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22850 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Gabe Black <gabeblack@google.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2019-12-13dev-virtio,configs: expose 9p diod virtio on ARMCiro Santilli
9p allows the guest Linux kernel to mount a host directory into the guest. This allows to very easily modify test programs after a run at the end of boot, without the need to re-insert the changes into a disk image. It is enabled on both fs.py and fs_bigLITTLE.py with the --vio-9p option. Adapted from code originally present on the wiki: http://gem5.org/WA-gem5 As documented in the CLI option help, the current setup requires the guest to know the full path to the host share, which is annoying, but overcoming that would require actually parsing a bit of the protocol rather than just forwarding everything to diod. Change-Id: Iaeb1ed185dccfa8332fe6657a54e7550f64230eb Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22831 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-12-13dev-virtio: VIO9P turns on diod verbose output with -d 1Ciro Santilli
Change-Id: I97e5762f4aca384068b87e22902e071fa3014ceb Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22829 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu> Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
2019-12-13dev-virtio: don't set the 9p default rootCiro Santilli
It is better to force users to explicitly set this argument, since it is unlikely that we will find one safe option for all users. Change-Id: I612520a44efd205a029a40cd13402584d16e1d88 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22828 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2019-12-13dev-virtio: use diod basename as the default 9p pathCiro Santilli
This allows diod to be present anywhere in the PATH by default, which works because we are already using execlp. Change-Id: I9d0b6c9a75f32cf0cb5d8f52bb00c465e4d43e1b Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22827 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2019-12-12mem: Encapsulate mapping gem5 to host address spaceDaniel R. Carvalho
Create a function to encapsulate mapping an address in gem5's address space to the host's address space. The returned value can be used to access the contents of the given address. As a side effect, make the local variable hostAddr use snake_case to comply with gem5's coding style. Change-Id: I2445d3ab4c7ce5746182b307c26cbafc68aa139c Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22610 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-12-12mem-cache: Move unused prefetches counter updateDaniel R. Carvalho
The number of unused prefetches should be updated every time a block is invalidated, therefore we move the update to within the corresponding function. Change-Id: If3ac2ea43611525bd3c36d628d88382042fcb7dc Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18908 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2019-12-12python: Convert terminal escape sequences to strings.Gabe Black
In python 3, the curses escape sequences are bytes objects and not strings, making them unsuitable to concatenate to strings which are being print()-ed. This uses the decode() method to turn them from bytes objects into string objects, assuming they represent UTF-8. In python 2, bytes objects and strings are treated interchangeably, and so this isn't necessary. Change-Id: Ifc5d788e1c62751090a350d3a064e89f434559e8 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23265 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-12-11arch-arm: Always initialize SVE memDataGiacomo Travaglini
Some compilers will produce a warning when using an uninitialized memData. JIRA: https://gem5.atlassian.net/browse/GEM5-196 Change-Id: I19e197b15729a03da546a0188917a9b3e7bf31b7 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23525 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-12-11arch-arm: Avoid creating an empty byteEnable vectorGiacomo Travaglini
This behaviour will be forbidden in following patches. Instead, create an all true vector. JIRA: https://gem5.atlassian.net/browse/GEM5-196 Change-Id: I61d2852610281f2d7c7a669dcb4d2728be194f52 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23524 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-12-11cpu: Replace empty byteEnable check with Request::isMaskedGiacomo Travaglini
This should be the interface to be used to check if the request has some masked bytes. JIRA: https://gem5.atlassian.net/browse/GEM5-196 Change-Id: I1ab5fd266c7b63a928aada32ae6d4f7fa915f2b6 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23523 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-12-11cpu: Fix coding style (byteEnable->byte_enable)Giacomo Travaglini
Change-Id: I2206559c6c2a6e6a0452e9c7d9964792afa9f358 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23282 Maintainer: Jason Lowe-Power <jason@lowepower.com> Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
2019-12-11cpu: Add byteEnable assertions to readMem and initateMemReadGiacomo Travaglini
Those are already present in writeMem; looking for consistency Change-Id: Ib85e0db228bc73e3ac64155d1290444cf6864a8c Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23281 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br> Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu> Tested-by: kokoro <noreply+kokoro@google.com> Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
2019-12-10sim,arch: Collapse the ISA specific versions of m5Syscall.Gabe Black
The x86 version doesn't do anything x86 specific, and so can be used generically in sim/pseudo_inst.(hh|cc) Jira Issue: https://gem5.atlassian.net/browse/GEM5-187 Change-Id: I46c2a7d326bd7a95daa8611888051c180e92e446 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23177 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com>
2019-12-10arch,cpu,sim: Push syscall number determination up to processes.Gabe Black
The logic that determines which syscall to call was built into the implementation of faults/exceptions or even into the instruction decoder, but that logic can depend on what OS is being used, and sometimes even what version, for example 32bit vs. 64bit. This change pushes that logic up into the Process objects since those already handle a lot of the aspects of emulating the guest OS. Instead, the ISA or fault implementations just notify the rest of the system that a nebulous syscall has happened, and that gets propogated upward until the process does something with it. That's very analogous to how a system call would work on a real machine. When a system call happens, the low level component which detects that should call tc->syscall(&fault), where tc is the relevant thread (or execution) context, and fault is a Fault which can ultimately be set by the system call implementation. The TC implementor (probably a CPU) will then have a chance to do whatever it needs to to handle a system call. Currently only O3 does anything special here. That implementor will end up calling the Process's syscall() method. Once in Process::syscall, the process object will use it's contextual knowledge to determine what system call is being requested. It then calls Process::doSyscall with the right syscall number, where doSyscall centralizes the common mechanism for actually retrieving and calling into the system call implementation. Jira Issue: https://gem5.atlassian.net/browse/GEM5-187 Change-Id: I937ec1ef0576142c2a182ff33ca508d77ad0e7a1 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23176 Maintainer: Gabe Black <gabeblack@google.com> Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Brandon Potter <Brandon.Potter@amd.com>
2019-12-10x86: Stop manually clearing RFLAGS.RF after a system call.Gabe Black
The system call stub KVM uses in SE mode to call the system call pseudo instruction which ultimately calls m5Syscall already uses sysret, and the implementation of sysret clears both the RF and VM bits itself. There's no reason to do that again explicitly here. Jira Issue: https://gem5.atlassian.net/browse/GEM5-187 Change-Id: Id7b5417564e3f3492ba6efb8ed36fab2f4c38e09 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23175 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com>
2019-12-10arch: Get rid of the now unused setSyscallArg.Gabe Black
Setting syscall args isn't really something we need to do in gem5, since that will be taken care of by the code actually calling the syscall. We just need to be able to retrieve the value it put there. Jira Issue: https://gem5.atlassian.net/browse/GEM5-187 Change-Id: I0bb6d5d0207a7892414a722b3788cb70ee509582 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23174 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com>
2019-12-10arch: Stop using setSyscallArg to set argc and argv.Gabe Black
In Alpha and MIPS, the argc and argv values should be in what happens to be the first and second syscall argument registers, but that's not by definition. The process objects of both those ISAs know what registers to use intrinsically, so there's also no reason to call out to a helper method which acts as a part of the Process's interface to the rest of gem5. Jira Issue: https://gem5.atlassian.net/browse/GEM5-187 Change-Id: Id8fa38ab1fc2ac6436e94ad41303439973fded10 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23173 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com>
2019-12-10sim: Add a wrapper/subclass for SyscallDesc which uses GuestABI.Gabe Black
This will let system call implementations take arguments naturally, and centrally defined, potentially complex, and ISA/context specific mechanisms will automatically gather the arguments and store any result. Jira Issue: https://gem5.atlassian.net/browse/GEM5-187 Change-Id: I68d265e0bab5de372ba975e4c7e9bb2d968c80af Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23172 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com>
2019-12-10sim: Add a mechanism to translate ABIs to call host funcs from a TC.Gabe Black
The guest ABI is specified as a template parameter. This makes it possible for host simcall handlers to be called through different ABIs which might be from different ISAs, or might be from different contexts within the same ISA (32 vs 64 bit, syscall vs. function vs. pseudo instrunction vs. semihosting call). Jira Issue: https://gem5.atlassian.net/browse/GEM5-187 Change-Id: I66a0f558e9c1f70a142b69b0dd95bd71e41d898b Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23171 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com>
2019-12-10sim: Get rid of the now unused SyscallDesc flags and methods.Gabe Black
Jira Issue: https://gem5.atlassian.net/browse/GEM5-187 Change-Id: Icee18a4bd77a346d7f82ef4988651b753392d51e Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23170 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com>
2019-12-10arch: Use ignoreWarnOnceFunc instead of the WarnOnce flag.Gabe Black
Jira Issue: https://gem5.atlassian.net/browse/GEM5-187 Change-Id: I9bbffcc74ec4f3df4effa5c50f0a4a688c5b6016 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23169 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com>
2019-12-10sim: Reintroduce the ignoreWarnOnceFunc syscall handler.Gabe Black
Instead of just using warn_once, we'll gate each warning on a bool which is associated with the syscall desc pointer. To avoid having to keep warn once bookkeeping in every syscall desc, we put it in a map which is looked up at runtime. Jira Issue: https://gem5.atlassian.net/browse/GEM5-187 Change-Id: I1dcce48de91b8a635f9f3df3bfc0ed6ba1291c4f Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23168 Maintainer: Gabe Black <gabeblack@google.com> Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Brandon Potter <Brandon.Potter@amd.com>
2019-12-10sim: Make the syscalls use the SyscallReturn suppression mechanism.Gabe Black
This, among other things, prevents them from needing to toggle global flags in the syscall desc table to control local behavior. Jira Issue: https://gem5.atlassian.net/browse/GEM5-187 Change-Id: Idcef23766084f10d5205721b54a6768a850f7eb9 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23167 Maintainer: Gabe Black <gabeblack@google.com> Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Brandon Potter <Brandon.Potter@amd.com>
2019-12-10dev-arm: GenericTimer, configurable base and low freqsAdrian Herrera
Architecture states the system counter has a fixed base frequency provided in the first entry of the frequency modes table. Optionally, other lower frequencies may be specified in consecutive entries. This patch adds configurable frequencies to the GenericTimer model. The default base frequency is kept as the one that was previously hardcoded for backwards compatibility. The table is not recommended to be updated once the system is running. Change-Id: Icba0b340a0eb1cbb47dfe7d7e03b547af4570c60 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22425 Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-12-10dev-arm: GenericTimer, freq as 32-bit valueAdrian Herrera
The System Counter frequency is now a 32-bit value. This is consistent with CNTFRQ and CNTFRQ_EL0 register sizes. Change-Id: I39886a3767adbe9c58887b8b6d5f30ebc6035bcc Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22424 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-12-10arch-arm: Disambuiguate NumFloatV7ArchRegs usageGiacomo Travaglini
Sometimes NumFloatV7ArchRegs is used to specify the maximum number of AArch32 floating point registers. Sometimes it is just used for indexing a free register storage to be used by microcode. In that scenario, VecSpecialElem should be used, which is a index to the first available non architectural register for floating point. Change-Id: I4e84740701f0e7041cf1acad2afed471361c423a Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23107 Tested-by: kokoro <noreply+kokoro@google.com>
2019-12-10arch-arm: Unify VLdmStm behaviour when reg out of indexGiacomo Travaglini
The generic VLdmStm class (modelling A32 VLDM/VSTM) is handling a wrong register list in a inconsistent way. Some instructions are opting for being decoded as Unknown, while others handle it inside the macro instruction constructor by manually adjusting the reglist. Those are two valid implementation of the CONSTRAINT UNPREDICTABLE behaviour (1 and 3): "If regs > 16 || (d+regs) > 32 , then one of the following behaviors must occur: 1) The instruction is UNDEFINED . 2) The instruction executes as NOP . 3) One or more of the SIMD and floating-point registers are UNKNOWN . If the instruction specifies writeback, the base register becomes UNKNOWN . This behavior does not affect any general-purpose registers." This patch unfies the behaviour by always opting for option 1) over 3) Change-Id: I4f98409243d5a2ec64113fe9c87e961a391abe94 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Ciro Santilli <ciro.santilli@arm.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23106 Tested-by: kokoro <noreply+kokoro@google.com>
2019-12-10arch-arm: Fix NumVecV7ArchRegs value (64->16)Giacomo Travaglini
In armv7 there are 16 only quadword (vector) registers which are usable by SIMD instructions (Q0-Q15). Those completely overlap with the 32 double word registers (D0-D31). NumVecV7ArchRegs = 16; // Q0-Q15 Change-Id: Id8fee1064d60dcfa54f273fa7d579a20c0087835 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23105 Tested-by: kokoro <noreply+kokoro@google.com>
2019-12-10arch-arm: Reorder arch/arm/registers.hh constantsGiacomo Travaglini
This is putting some order in the constants definition, respecting the description which divides: * Constants Related to the number of registers (example: const int NumFloatRegs = 0) from: * Semantically meaningful register indices (to indicate special registers) (example: const int INTRLVREG0 = NumVecV8ArchRegs + NumVecSpecialRegs) Change-Id: I1760b7f786b6f6becbe8ab445e65fc3fa17206cb Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23104 Tested-by: kokoro <noreply+kokoro@google.com>
2019-12-10arch-arm: Replace NumFloatV8ArchRegs with NumVecV8ArchRegsGiacomo Travaglini
gem5-ARM is not using floatRegs anymore and moved towards the vecRegs register file (which is used for SIMD&FP + SVE instructions) Change-Id: I41cfbe10565e4e0db838f98626310a5b14edadb9 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23103 Tested-by: kokoro <noreply+kokoro@google.com>
2019-12-09tests: AArch64 Linux as quick regressions (instead of AArch32)Giacomo Travaglini
NOTE: Following the discussion on the current patch review, some regressions have been moved to the long list (realview64-simple-atomic and realview64-simple-timing) in order to reduce computation time. These should be moved back to the quick list as soon as we get more computing power. Change-Id: I07b98c968ad35bf4c7b3646cb72d870e6b07b0d6 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22686 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
2019-12-09mem: Add Request::isMasked to check for byte strobingGiacomo Travaglini
This is trying to overcome the following problem: At the moment a memory request with a non empty byteEnable mask will be considered masking even if all elements in the vector are true. Change-Id: I16ae2c0ea8c3f3370e397bab9d79d6d60c3784bd Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23284 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu> Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-12-09mem: Add byteEnable copy to Request copy constructorGiacomo Travaglini
Change-Id: Ie97543e62524bb244ae65eef096411af4605c175 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23283 Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br> Tested-by: kokoro <noreply+kokoro@google.com>
2019-12-09tests: Increase jenkins test timeout to 4 hours.Rahul Thakur
Change-Id: I11d36a429254df01a46040325baff5b7d18e22b3 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23463 Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu> Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu> Tested-by: kokoro <noreply+kokoro@google.com>
2019-12-08arch-riscv: set MaxMiscDestRegs to 2Alec Roelke
In an earlier patch, the FCSR was split into its two components, FRM and FFLAGS, causing explicit writes to FCSR to incur two CSR writes. With the O3 CPU model, which defers them both to later, this creates a bug where an assertion that the number of CSR writes must be less than MaxMiscDestRegs fails because that constant is 1. This patch sets it to 2 so the O3 CPU is compatible with this scheme. Change-Id: Ic3413738c4eebe9f127980d0d0af5033d18468e7 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23220 Reviewed-by: Alec Roelke <alec.roelke@gmail.com> Maintainer: Alec Roelke <alec.roelke@gmail.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-12-07scons: Set the partial linking group for EXTRAS dirs.Gabe Black
Partial linking heuristically links together files in the same directory by setting a special automatic tag. That tag needs to also be maintained when scanning EXTRAS dirs so that they don't all get lumped in with the last normal directory that was processed. Change-Id: I2408ea0a1eeffcf6d9994c36415a35760b225b17 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23300 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-12-07scons: Fixes to improve python 3 support.Gabe Black
Some simple fixes to improve python 3 compatability in scons. Change-Id: I89aba6ed9d73ee733307c57e033c636029d9cb7a Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23264 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-12-06util: Add a git commit-msg hookDaniel R. Carvalho
Add a git commit-msg hook that verifies that commit messages follow gem5 guidelines. Commit messages must contain the following components: <gem5_tags>: <title> <description> <patch_tags> <gem5_tags> are comma separated keywords (found in MAINTAINERS) that describe which sections of gem5 are being modified by the patch. Two special keywords can also be used to imply that the author is looking for feedback on the way their commit was implemented (RFC), and to inform that the commit is a work in progress (WIP). <title> A short and concise description of the commit without trailing whitespaces <description> is an optional (yet highly recommended) detailed description of the objective of the commit. <patch_tags> describe the metadata of the commit, and most of them are automatically added by Gerrit. Change-Id: Ib6fb6edf6d1417bfda23729b35c5b8ed44d2cf51 Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21739 Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu> Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu> Tested-by: kokoro <noreply+kokoro@google.com>
2019-12-06kvm,arm: Update the KVM ARM v8 CPU to use vector regs.Gabe Black
The exact mapping of the KVM registers and the gem5 registers is direct and may not actually be correct. Change-Id: Idb0981105c002e65755f8dfc315dbb95ea9370df Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23402 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-12-06arch-riscv: fix asmtest concurrent issues.Xin Ouyang
riscv asmtest uses multiprocessing.Pool to run multiple gem5 processes concurrently. By using gem5 default options, processes will fail because: - accessing to the same m5out directory - listening too many remote gdb ports at the same time This will set independent m5out directories and disable remote gdb ports for asmtest gem5 processes. Change-Id: Ie4c81232210568cd1945adc2b99eebc019d705b6 Signed-off-by: Xin Ouyang <xin.ouyang@streamcomputing.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22863 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Alec Roelke <alec.roelke@gmail.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-12-05arch-x86: missing override specifierAndrea Mondelli
Change-Id: I5a6db4632ec5b670cbfeb7d52190a7545c0b985f Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23380 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-12-05arch-x86: Adding LDDQU instructionmarjanfariborz
Tested with simple c binaries. Signed-off-by: marjanfariborz <mfariborz@ucdavis.edu> Change-Id: I2f0852b136f966381d29af523e8ffdbca795afcd Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23262 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-12-04sim: Add a suppression mechanism to the SyscallReturn class.Gabe Black
It makes more sense to specify whether something should be returned based on the return, not intrinsically on the syscall. This is especially true in cases like execve where the expected behavior is not constant. Jira Issue: https://gem5.atlassian.net/browse/GEM5-187 Change-Id: I95b53b6d69445c7a04c0049fbb0f439238d971e8 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23166 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-12-04sim: Small style fixes in sim/syscall_return.hh.Gabe Black
Jira Issue: https://gem5.atlassian.net/browse/GEM5-187 Change-Id: I485004843393c2e10c1ff4dbd84fc30ca4fd490c Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23165 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-12-04sim: Change the syscall executor to a std::function.Gabe Black
This will enable using other types of callable like a lambda. Jira Issue: https://gem5.atlassian.net/browse/GEM5-187 Change-Id: If9f7176205492830824b5fe3c00f2c7710f57f70 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23164 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Gabe Black <gabeblack@google.com> Tested-by: kokoro <noreply+kokoro@google.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-07-04 06:30:19 +0000