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AgeCommit message (Expand)Author
2019-10-25cpu,sim: Get rid of a bunch of conditional compilation for PCEvents.Gabe Black
2019-10-25cpu: Don't print the CPU name when a (Break|Panic)PCEvent happens.Gabe Black
2019-10-25cpu: Pass the address to check into the PCEventQueue service method.Gabe Black
2019-10-25sim: Make the System object a PCEventScope.Gabe Black
2019-10-25cpu: Stop checking for PC changes when servicing a PCEventQueue.Gabe Black
2019-10-25cpu: Create a PCEventScope class to abstract the scope of PCEvents.Gabe Black
2019-10-24tests: Added GTests for base/str.ccBobby R. Bruce
2019-10-24cpu, sim-se: don't wake up threads that are awake in futexCiro Santilli
2019-10-24sim-se: fix futexFunc TGT_FUTEX_WAIT always selects bitsetCiro Santilli
2019-10-23fastmodel: Add string constructors which delegate to const char * ones.Gabe Black
2019-10-23cpu: Apply the ARM TLB rework to the O3 checker CPU.Gabe Black
2019-10-23arch: Drop sysctl support if built against glibcTommaso Marinelli
2019-10-22configs: Clean setupBootLoader signatureGiacomo Travaglini
2019-10-22configs: Do not assume bootmem is a System childGiacomo Travaglini
2019-10-22dev-arm, configs: Using _on_chip_memory for on chip memoryGiacomo Travaglini
2019-10-21cpu: Apply the ARM TLB rework to the checker CPU.Gabe Black
2019-10-21misc: Add Giacomo Travaglini as an Arm maintainerAndreas Sandberg
2019-10-19cpu,arm: Push the stage 2 MMUs out of the CPU into the TLBs.Gabe Black
2019-10-19arch: Remove the "interrupts.hh" switching header file.Gabe Black
2019-10-19arch: Make a base class for Interrupts.Gabe Black
2019-10-18dev-arm: Check for gem5 extensions in GicV2Tiago Muck
2019-10-18tests: Added GTests for base/bitfield.hhBobby R. Bruce
2019-10-18arch: Get rid of the unused GenericTLB.Gabe Black
2019-10-18cpu: Turn the stage 2 ARM MMUs from params to children.Gabe Black
2019-10-18x86: Turn the local APIC Interrupts class into a SimObject.Gabe Black
2019-10-18tests: Added GTests for base/atomicio.ccBobby R. Bruce
2019-10-18base: Add classes that encapsulate a channel addressAndreas Sandberg
2019-10-18mem: Delete the MessageReq and MessageResp memory commands.Gabe Black
2019-10-17arm: Don't force the ArmISA::TLB in vtophys.cc.Gabe Black
2019-10-17cpu: Clean up some style issues in pc_event.(hh|cc).Gabe Black
2019-10-17cpu: Get rid of load count based events.Gabe Black
2019-10-16base: Add addIntlvBits to AddrRangeAndreas Sandberg
2019-10-16base: Using scoped string in DPRINTFNRGiacomo Travaglini
2019-10-16base: Fix gem5.fast compilationGiacomo Travaglini
2019-10-16arch,base,sim: Move Process loader hooks into the Process class.Gabe Black
2019-10-15x86: Use a std::function to handle MSI completion.Gabe Black
2019-10-15arch,base: Restructure the object file loaders.Gabe Black
2019-10-15cpu: Delete the unused sched_break_pc(_sys) functions.Gabe Black
2019-10-15arch-x86: Make LFENCE a serializing instructionIsaac Richter
2019-10-15dev-arm: Carve out a portion of VExpress_GEM5 for the bootloaderGiacomo Travaglini
2019-10-15configs: Add simpleSystem helper to generate devices.SimpleSystemGiacomo Travaglini
2019-10-15sim,cpu: Get rid of the unused instEventQueue.Gabe Black
2019-10-15x86: De-x86ify the IntMasterPort.Gabe Black
2019-10-14Tests: Added GTests for base/callback.ccBobby R. Bruce
2019-10-14x86: Simplify and consolidate the code that assembles an MSI on x86.Gabe Black
2019-10-14fastmodel: Expose all CPU communication ports from the GIC.Gabe Black
2019-10-14misc: Updating contributing.md to discuss Gerrit guidelinesBobby R. Bruce
2019-10-13mem-cache: set the second chance to false when inserting a blockMingyuan
2019-10-12mem-cache: Fixed a bug in MRU replacement policyMingyuan
2019-10-12x86: Stop using and delete the x86 IntDevice class.Gabe Black
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