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2019-10-25cpu: Get rid of the serviceInstCountEvents method.Gabe Black
This was useful when transitioning away from the CPU based comInstEventQueue, but now that objects backing the ThreadContexts have access to the underlying comInstEventQueue and can manipulate it directly, they don't need to do so through a generic interface. Getting rid of this function narrows and simplifies the interface. Change-Id: I202d466d266551675ef6792d38c658d8a8f1cb8b Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22113 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-10-25fastmodel: Use getCurrentInstCount for totalInsts().Gabe Black
This had been using a custom totalInsts method on the iris ThreadContext, but since that's equivalent to what the totalInsts method does only through a different mechanism, we can drop that and use getCurrentInstCount instead. Change-Id: I058fec13e81f28285281e136635d53a2e849cb47 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22112 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-10-25fastmodel: Implement getCurrentInstCount.Gabe Black
This uses the step counter the iris API provides. Change-Id: Ic916888fa256d0aa65042d3e6695d9bf4ba32c86 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22111 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-10-25cpu: Switch off of the CPU's comInstEventQueue.Gabe Black
This switches to letting the ThreadContexts use a thread based/local comInstEventQueue instead of falling back to the CPU's array. Because the implementation is no longer shared and it's not given where the comInstEventQueue (or other implementation) should be accessed, the default implementation has been removed. Also, because nobody is using the CPU's array of event queues, those have been removed. Change-Id: I515e6e00a2174067a928c33ef832bc5c840bdf7f Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22110 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-10-25cpu: Access inst events through ThreadContext instead of the CPU.Gabe Black
Also delete the CPU interface. Change-Id: I62a6b0a9a303d672f4083bdedf393f9f6d07331f Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22109 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-10-25cpu: Delegate comInstEventQueue methods to the ThreadContexts.Gabe Black
These then just use the comInstEventQueue array from the CPU, but soon they will actually be self contained and allow the thread context to use whatever mechanism it wants. Also, now that the thread contexts need to exist before instruction count based events can be scheduled, setting up max instruction based events needs to happen in init after the CPU subclasses have had a chance to set up the threadContexts vector. Change-Id: I34bb401633d277a60be74e30d5a478a149b972ea Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22108 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-10-25cpu: Make accesses to comInstEventQueue indirect through methods.Gabe Black
This lets us move the event queue itself around, or change how those services are provided. Change-Id: Ie36665b353cf9788968f253cf281a854a6eff4f4 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22107 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Gabe Black <gabeblack@google.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-10-25cpu,sim: Delegate PCEvent scheduling from Systems to ThreadContexts.Gabe Black
The System keeps track of what events are live so new ThreadContexts can have the same set of events as the other ThreadContexts. Change-Id: Id22bfa0af7592a43d97be1564ca067b08ac1de7c Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22106 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Gabe Black <gabeblack@google.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-10-25cpu: Make the ThreadContext a PCEventScope.Gabe Black
Both the thread and system's PCEventQueue are checked when appropriate. Change-Id: I16c371339c91a37b5641860d974e546a30e23e13 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22105 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Gabe Black <gabeblack@google.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-10-25cpu,sim: Get rid of a bunch of conditional compilation for PCEvents.Gabe Black
These can now be built without referring to anything in ThreadContext and so can be built even with the NULL ISA. This means the pcEventQueue can be unconditionally built into the System class. Even though the pcEventQueue is going away, this still makes it possible for System to be a PCEventScope unconditionally. Change-Id: Ia342bb7972b1b5ce95033176d72af4bfa343560f Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22104 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-10-25cpu: Don't print the CPU name when a (Break|Panic)PCEvent happens.Gabe Black
This requires reaching into the threadcontext to access the CPU pointer, and also isn't all that useful since it's more important what event happened, not what CPU happened to be running the code at that time. Change-Id: I368707c804dff9bd349f3261bdcd08be55c5d04a Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22103 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Gabe Black <gabeblack@google.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-10-25cpu: Pass the address to check into the PCEventQueue service method.Gabe Black
This prevents having to access it from within the ThreadContext. Change-Id: I34f5815a11201b8fc41871c18bdbbcd0f40305cf Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22102 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Gabe Black <gabeblack@google.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-10-25sim: Make the System object a PCEventScope.Gabe Black
This abstracts away the raw PCEventQueue managed by the System. Change-Id: I04d773e6be90a891884a76841f15c3eecd5796ed Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22101 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Gabe Black <gabeblack@google.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-10-25cpu: Stop checking for PC changes when servicing a PCEventQueue.Gabe Black
First of all, this would arbitrarily skip events based on when they were encountered in the queue. Second, this is one of the three places where the ThreadContext is actually accessed in pc_event.cc. By removing this and the other uses, this file can be included even when using the NULL ISA, and a lot of #ifdefs can be removed. Change-Id: If81f5e9ff9d3f9833145fec0b6062b4bda8d2e47 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22100 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-10-25cpu: Create a PCEventScope class to abstract the scope of PCEvents.Gabe Black
This abstraction will allow scheduling PCEvents for a particular ThreadContext, all contexts on a CPU, all contexts in a system, etc., and delegates scheduling and removing events to each particular scope. Right now the PCEventQueue is the only implementor of the PCEventSCope interface. Change-Id: I8fb62931511136229915c2e19d36aae7ffdec9df Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22099 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-10-24tests: Added GTests for base/str.ccBobby R. Bruce
Adding these tests supercedes the unittest/strnumtest.cc and unittest/tokentest.cc tests. They have thereby been removed. Function "to_number" in base/str.hh previously failed to cast negative float/double numbers. This was due to the use of std::numeric_limits<T>::min() instead of std::numeric_limits<T>::lowest() to determine whether a string-to-float/double conversion was "Out of range". Tests "StrTest.ToNumberFloatNegative" and "StrTest.ToNumberDoubleNegative" exposed this bug. It has been fixed. Methods "split_first" and "split_last" in base/str.hh have had their documentation updated to remove abiguity in their functionality. Change-Id: I16e0fe40d884e22dd010db4045857eb6e7f33d4a Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22084 Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br> Maintainer: Jason Lowe-Power <jason@lowepower.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-10-24cpu, sim-se: don't wake up threads that are awake in futexCiro Santilli
FutexMap::wakeup is called when the futex(TGT_FUTEX_WAKE syscall is done. FutexMap maintains a list of sleeping threads for each futex address added on FutexMap::suspend, and entries are removed from the list at FutexMap::wakeup. The problem is that this system was not taking into account that threads can be woken up by memory accesses to locked addresses via the path: SimpleThread::activate BaseSimpleCPU::wakeup AbstractMemory::checkLockedAddrList AbstractMemory::access DRAMCtrl::recvAtomic CoherentXBar::recvAtomicBackdoor SimpleExecContext::writeMem which happens on trivial pthread examples on ARM at least. The instruction that locked memory in those test cases was LDAXR. This could lead futex(TGT_FUTEX_WAKE to awake a thread that is already awake but is first on the sleeping thread list, instead of a sleeping one, which can lead all threads to incorrectly sleep and in turn to "simulate() limit reached". To implement this, ThreadContext::activate return now returns a boolean that indicates if the state changed. suspend and halt are also modified to also return a boolean in the same case for symmetry, although this is not strictly necessary for the current patch. Change-Id: Ia6b4d3e6148c64721d810b8f1fffaa208a394b06 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21606 Reviewed-by: Brandon Potter <Brandon.Potter@amd.com> Maintainer: Brandon Potter <Brandon.Potter@amd.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-10-24sim-se: fix futexFunc TGT_FUTEX_WAIT always selects bitsetCiro Santilli
Change-Id: I3e2bd1dd34d7cc00b2685547ab74b56bd8126128 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21605 Reviewed-by: Brandon Potter <Brandon.Potter@amd.com> Maintainer: Brandon Potter <Brandon.Potter@amd.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-10-23fastmodel: Add string constructors which delegate to const char * ones.Gabe Black
Change-Id: I22d88111409fc477c135b15c8f898adad4f6d4ab Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21502 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
2019-10-23cpu: Apply the ARM TLB rework to the O3 checker CPU.Gabe Black
The TLBs now create the stage 2 MMUs as children, and since those are specialized for instruction and data, the CPU needs to use ArmITB or ArmDTB instead of ArmTLB which is the base class without an MMU. This was changed for the BaseCPU and SimpleCPU checker already, but the TLBs are added in the O3 checker CPU as well. Change-Id: I498f247f376c8721fb70ce26c0f1b0815b12fe2d Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22039 Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-10-23arch: Drop sysctl support if built against glibcTommaso Marinelli
Since glibc 2.30 the sysctl() function has been declared deprecated and it will be deleted in future versions. This patch removes the support for the sysctl system call in SE mode (which is currently serviced calling the sysctl() function) if gem5 is built against glibc, keeping it with other libc implementations, as a temporary measure to prevent the generation of a compilation error. Note that this system call in gem5 is only supported for the arm/freebsd architecture. Change-Id: Ie5fcb983d15c0a27c7820d24250d7ae5dbe12355 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21519 Reviewed-by: Brandon Potter <Brandon.Potter@amd.com> Maintainer: Brandon Potter <Brandon.Potter@amd.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-10-22configs: Clean setupBootLoader signatureGiacomo Travaglini
This is because the bus parameter is not used anymore Change-Id: I27aa8cc064904a6e3e0376f61eb7db74ea1a4d6c Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22002 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2019-10-22configs: Do not assume bootmem is a System childGiacomo Travaglini
As far as I can see bootmem is used in Arm systems only. With https://gem5-review.googlesource.com/c/public/gem5/+/21604 bootmem has been moved from system to system.realview. This patch fix things by removing the assumption that the bootmem SimObject lives under the system. It is now trying to getattr a reference of the bootmem. It is the ISA specific system builder's duty to bind the bootmem reference (_bootmem) to the real bootmem object Change-Id: I1e7405b5cb186de13c44bfd93fb4c8a1a5447f24 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22001 Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-10-22dev-arm, configs: Using _on_chip_memory for on chip memoryGiacomo Travaglini
This patch is pulling the on-chip memory outside of the on_chip_devices list. The external interface will be more or less the same: configuration scripts will still use the attachOnChipIO method; a new kw argument has been added in order to store mem_ports. We want to provide to on-chip memory the same mechanism used when collecting on-chip dma ports. This is needed when using Ruby, since we need to pass a non None mem_ports to prevent the bootmem to be wired to the bus. Change-Id: Ifc519c3072dc5de1530772c70c80dc2094e2c54c Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22000 Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-10-21cpu: Apply the ARM TLB rework to the checker CPU.Gabe Black
The TLBs now create the stage 2 MMUs as children, and since those are specialized for instruction and data, the CPU needs to use ArmITB or ArmDTB instead of ArmTLB which is the base class without an MMU. This was changed for the BaseCPU already, but the TLBs are added in the checker CPU as well. Change-Id: Ide8ce950622b40f69c37bbe2ea0d22295b76d7a6 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21979 Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-10-21misc: Add Giacomo Travaglini as an Arm maintainerAndreas Sandberg
I have been delegating a lot of changes to Giacomo T for a long time, making him a de facto Arm co-maintainer. Make this official by adding him to the list of maintainers. Change-Id: I69c53316e2fc6ca162d07ac2d167ac2ae2b6bbee Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21899 Maintainer: Jason Lowe-Power <jason@lowepower.com> Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
2019-10-19cpu,arm: Push the stage 2 MMUs out of the CPU into the TLBs.Gabe Black
This regularizes the TLB setup in the CPU so that ARM is no longer a special case with extra objects. Change-Id: I739b82578ff74f8f9777cd7e34cd5227b47b186c Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21842 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2019-10-19arch: Remove the "interrupts.hh" switching header file.Gabe Black
That switching header is no longer necessary since everything outside of the ISA can use the BaseInterrupts class. Change-Id: Ie3ed45c38fec24234ff51fb05ba94f6f3cd02afd Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20832 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2019-10-19arch: Make a base class for Interrupts.Gabe Black
That abstracts the ISA further from the CPU, getting us a small step closer to being able to build in more than one ISA at a time. Change-Id: Ibf7e26a3df411ffe994ac1e11d2a53b656863223 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20831 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2019-10-18dev-arm: Check for gem5 extensions in GicV2Tiago Muck
Using GicV2 without setting the gem5_extensions parameter in a config with more than 8 is not allowed to prevent overflow of the 8-bit mask. Change-Id: I780c6985e8f44ed780b4f74f9a27805124e23a7b Signed-off-by: Tiago Mück <tiago.muck@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19288 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-10-18tests: Added GTests for base/bitfield.hhBobby R. Bruce
In addition to the tests, a more detailed explanation of how "insertBits(..)" functions has been included in its doxygen documentation. The previous explanation was ambigious and led to confusion. Change-Id: I2ae8608733ebaa8f8f726cbb3a2cd8639b69c6b7 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21700 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Gabe Black <gabeblack@google.com> Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2019-10-18arch: Get rid of the unused GenericTLB.Gabe Black
Nothing is using it, and it's actually not use*able* at the moment because it doesn't have implementations for all the pure virtual methods that exist in the BaseTLB class. Change-Id: I03d47c2e116f354c7247a2fa19a9f33dfe4c5eec Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21841 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-10-18cpu: Turn the stage 2 ARM MMUs from params to children.Gabe Black
These aren't referred to in the C++, so there's no reason for them to be parameters. By making them children, they can still be modified, replaced wholesale, or even replaced by an entirely different object to, for instance, mask them when they're not needed. Change-Id: Ic7f144a3cd3d1fca12fec220918aa72af885f61c Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21839 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-10-18x86: Turn the local APIC Interrupts class into a SimObject.Gabe Black
It will no longer be a PioDevice or a ClockedObject, but will carry forward the little bits and pieces of those classes that it was using. Those are a PIO port for memory mapped register accesses, and a clock domain parameter for setting the apic tick frequency. This brings the x86 Interrupts class in line with the Interrupts of the other ISAs so that they can inherit from a standard base class. Change-Id: I6b25fa21911b39a756e0cf9408c5489a81d6ca56 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20829 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Brandon Potter <Brandon.Potter@amd.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-10-18tests: Added GTests for base/atomicio.ccBobby R. Bruce
Change-Id: I586a06c70f4e7331b4a31208ef7831e8473509c5 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21699 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-10-18base: Add classes that encapsulate a channel addressAndreas Sandberg
There are cases where the memory system needs to reason about channel-local addresses. These are currently represented using the Addr and AddrRange classes. This is not ideal since it doesn't provide any type safety when working with global addresses and channel-local addresses. This is particularly problematic when porting existing components to work in multi-channel configurations. This changeset introduces the new ChannelAddr and ChannelAddrRange classes. These classes encapsulate channel-local addresses in a contiguous address space. These can, for example, be used in a memory controller to represent a flat address space when calculating timings or in a sectored cache. Change-Id: I45d4061ebc8507a10d0a4577b28796dc5ec7a469 Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21600 Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu> Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-10-18mem: Delete the MessageReq and MessageResp memory commands.Gabe Black
Now that Message*Port is gone, there are no users of these two memory commands. They can now be deleted, simplifying the memory system slightly. Change-Id: If157dade4a3fb2610756c2ee81dc0c3fac670a26 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20824 Reviewed-by: Gabe Black <gabeblack@google.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Gabe Black <gabeblack@google.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-10-17arm: Don't force the ArmISA::TLB in vtophys.cc.Gabe Black
The only reason the TLB pointer is being cast to an ArmISA::TLB is so that it can call a version of translateFunctional which takes more arguments, when the standard version of translateFunctional just calls that underlying function with the same arguments. Change-Id: I3ffd3a8ecc2dda91ddca77f516e2b2ac7313a227 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21840 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
2019-10-17cpu: Clean up some style issues in pc_event.(hh|cc).Gabe Black
The record_t typedef isn't all that helpful, and is also not consistent with gem5 style. The map_t style is more useful but is also not compliant. This change eliminates the first typedef and replaces the second with a type called Map. There are some other small style fixups added in as well, like making the member variable pc_map pcMap. Change-Id: I8ffea529004fd6d5b42fdc60250804e2e4987e88 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21781 Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu> Maintainer: Gabe Black <gabeblack@google.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-10-17cpu: Get rid of load count based events.Gabe Black
This was initially added in 2003 and only supported in the simple CPUs. It's oddly specific since there are no other similar event queues for, for instance, stores, branches, system calls, etc. Given that this seems like a historical oddity which is only partially supported and would be very hard to support on more diverse CPU types like KVM or fast model which don't generally have hooks for counts of specific instruction types. Change-Id: I29209b7ffcf896cf424b71545c9c7546f439e2b9 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21780 Reviewed-by: Brandon Potter <Brandon.Potter@amd.com> Maintainer: Gabe Black <gabeblack@google.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-10-16base: Add addIntlvBits to AddrRangeAndreas Sandberg
This method performs the opposite operation of removeIntlvBits and can be used to transform a channel-local address to a global PA. Change-Id: I2fab587d7c094597e52422305775ac7f31efba34 Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21599 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br> Tested-by: kokoro <noreply+kokoro@google.com>
2019-10-16base: Using scoped string in DPRINTFNRGiacomo Travaglini
We would otherwise need to add a using namespace std wherever we use DPRINTFNR. Change-Id: I30bf9ba474408133abded66141f6dc96dfdba8d6 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21821 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu> Maintainer: Jason Lowe-Power <jason@lowepower.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-10-16base: Fix gem5.fast compilationGiacomo Travaglini
Change-Id: I86c83e8622ae5a88ff802ccb1cb919194c1251ef Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21820 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu> Maintainer: Jason Lowe-Power <jason@lowepower.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-10-16arch,base,sim: Move Process loader hooks into the Process class.Gabe Black
This code was originally in the ObjectFile class, but not all object files will become Processes. All Processes will ultimately come from ObjectFiles though, so it makes more sense to put that class there. Change-Id: Ie73e4cdecbb51ce53d24cf68911a6cfc0685d771 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21468 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Gabe Black <gabeblack@google.com> Tested-by: kokoro <noreply+kokoro@google.com> Maintainer: Gabe Black <gabeblack@google.com>
2019-10-15x86: Use a std::function to handle MSI completion.Gabe Black
This removes the recvResponse callback from the IntMasterPort, and makes it easier to handle the default case where we just need to clean up the Packet. Change-Id: I8bcbfee0aaf68b12310d773f925c399fc87ea65d Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20828 Maintainer: Gabe Black <gabeblack@google.com> Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Brandon Potter <Brandon.Potter@amd.com>
2019-10-15arch,base: Restructure the object file loaders.Gabe Black
This change creates a distinction between object files which hold executable code, and flat files which don't. The first type of files have entry points, symbols, etc., while the others are just blobs which can be shoved into memory. Rather than have those aspects but stub them out, this change creates a new base class which simply doesn't have them. This change also restructures the ELF loader since it's main function was quite long and doing multiple jobs. It stops passing the architecture and operating system to the ObjectFile constructor, since those might not be known at the very top of the constructor. Instead, those default to Uknown*, and then are filled in in the constructor body if appropriate. This removes a lot of plumbing that was hard to actually use in practice. It also introduces a mechanism to collect generic object file formats so that they can be tried one by one by the general createObjectFile function, rather than listing them all there one by one. It's unlikely that new types of object files will need to be added in a modular way without being able to modify the core loader code, but it's cleaner to have that abstraction and modularization like is already there for process loaders. Finally, to make it possible to share the code which handles zipped files for both true object files and also files which will be loaded into memory but are just blobs, that mechanism is pulled out into a new class called ImageFileData. It holds a collection of segments which are set up by the object file and may refer to regions of the original file, buffers maintained elsewhere, or even nothing to support bss-es. shared_ptr is used to make it easier to keep track of that information without having to do so explicitly or worry about deleting a buffer before everyone was done using it. Change-Id: I92890266f2ba0a703803cccad675a3ab41f2c4af Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21467 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Brandon Potter <Brandon.Potter@amd.com> Maintainer: Gabe Black <gabeblack@google.com>
2019-10-15cpu: Delete the unused sched_break_pc(_sys) functions.Gabe Black
Change-Id: I2adae2858897e665fd28cfe9de3fdcf95ffc2a2e Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21779 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-10-15arch-x86: Make LFENCE a serializing instructionIsaac Richter
According to the Intel SDM, no instruction following an LFENCE can begin execution until after the LFENCE has executed. (This is less strict than an actual serializing instruction, such as CPUID.) Serializing instructions (per intel SDM Volume 3A Chapter 8.3) ensure that no future instruction is fetched until after the serializing instruction is completed. By contrast, LFENCE (and other memory-ordering instructions) allows future instructions to have been fetched; it just prohibits them from being executed. Change-Id: If89fcb552192326ab69a581f57d71c95cf5d90e7 Signed-off-by: Isaac Richter <isaac.richter@rochester.edu> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/10321 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-10-15dev-arm: Carve out a portion of VExpress_GEM5 for the bootloaderGiacomo Travaglini
This patch is carving out a portion of VExpress_GEM5 memory for the bootloader. Prior to this patch this was only happening conditionally/dynamically via the setupBootLoader call. With this patch the region is always present and the setupBootLoader doesn't instantiate memory, it is only setting up some bootloader parameters. Change-Id: Iaa5cdf471b14e8faa37353a25631bf7c6fc64afc Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21604 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-10-15configs: Add simpleSystem helper to generate devices.SimpleSystemGiacomo Travaglini
This patch will make it possible to generate a SimpleSystem inheriting from a configurable base class. More practically it will be possible to inherit from a baremetal System (ArmSystem) rather than from a LinuxArmSystem Change-Id: I11553ae8045519059e159c555c6c9141bb4519b7 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21603 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
generated by cgit v1.2.3 (git 2.25.1) at 2025-02-18 07:22:18 +0000