| Age | Commit message (Collapse) | Author | |
|---|---|---|---|
| 2010-11-22 | IDE,X86: Fix IDE controller BAR configuration for x86. | Gabe Black | |
| 2010-11-20 | random: small comment about our random number generator and its origin | Nathan Binkert | |
| 2010-11-19 | SE: Fix simulating more than 4GB of RAM in SE mode | Ali Saidi | |
| This change removes some dead code in PhysicalMemory, uses a 64 bit type for the page pointer in System (instead of 32 bit) and cleans up some style. | |||
| 2010-11-19 | SCons: Fix compilation on OS X | Ali Saidi | |
| 2010-11-19 | SCons: Support building without an ISA | Ali Saidi | |
| 2010-11-18 | O3: Fix fp destination register flattening, and index offset adjusting. | Gabe Black | |
| This change makes O3 flatten floating point destination registers, and also fixes misc register flattening so that it's correctly repositioned relative to the resized regions for integer and floating point indices. It also fixes some overly long lines. | |||
| 2010-11-17 | Config: Change misleading "cycle" message to say "tick". | Gabe Black | |
| Most of the messages in the config scripts that report a time value already print "@ tick" followed by the current tick value, but a few were printing "@ cycle". Since this is a distinction that's frequently confusing to new users, this changes those message to the more accurate and consistent "@ tick". | |||
| 2010-11-15 | Stats: Update the O3 fetch stats for SPARC. | Gabe Black | |
| 2010-11-15 | O3: Make O3 support variably lengthed instructions. | Gabe Black | |
| 2010-11-15 | O3: reset architetural state by calling clear() | Ali Saidi | |
| 2010-11-15 | ARM: Add comment about the organization of the IT state register | Ali Saidi | |
| 2010-11-15 | Regressions: Update regressions for SIMD opclass changes | Ali Saidi | |
| 2010-11-15 | CPU/ARM: Add SIMD op classes to CPU models and ARM ISA. | Giacomo Gabrielli | |
| 2010-11-15 | ARM: Compile O3 CPU by default | Ali Saidi | |
| 2010-11-15 | O3: prevent a squash when completeAcc() modifies misc reg through TC. | Min Kyu Jeong | |
| This happens on ARM instructions when they update the IT state bits. Code and associated comment was copied from execute() and initiateAcc() methods | |||
| 2010-11-15 | ARM: Return an FailUnimp instruction when an unimplemented CP15 register is ↵ | Ali Saidi | |
| accessed. Just panicing in readMiscReg() doesn't work because a speculative access in the o3 model can end the simulation. | |||
| 2010-11-15 | SCons: Cleanup SCons output during compile | Ali Saidi | |
| 2010-11-15 | ARM: Update regressions for CLCD and KMI additions | Ali Saidi | |
| 2010-11-15 | ARM: Add a Keyboard Mouse Interface controller | William Wang | |
| 2010-11-15 | ARM: Implement a CLCD Frame buffer | William Wang | |
| 2010-11-15 | ARM: Add support for GDB on ARM | William Wang | |
| --HG-- rename : src/arch/alpha/remote_gdb.cc => src/arch/arm/remote_gdb.cc | |||
| 2010-11-15 | ARM: Make utility.hh meet style guidelines | Ali Saidi | |
| 2010-11-15 | ARM: Add support for a dumb IDE controller | Ali Saidi | |
| 2010-11-15 | ARM: Cache the misc regs at the TLB to limit readMiscReg() calls. | Ali Saidi | |
| 2010-11-15 | ARM: Add support for switching CPUs | Ali Saidi | |
| 2010-11-15 | ARM: Use the correct delete operator for RFE | Ali Saidi | |
| 2010-11-15 | ARM: Fix SRS instruction to micro-code memory operation and register update. | Ali Saidi | |
| Previously the SRS instruction attempted to writeback in initiateAcc() which worked until a recent change, but was incorrect. | |||
| 2010-11-15 | CPU: Fix bug when a split transaction is issued to a faster cache | Ali Saidi | |
| In the case of a split transaction and a cache that is faster than a CPU we could get two responses before next_tick expires. Add an event that is scheduled in this case and return false rather than asserting. | |||
| 2010-11-15 | ARM: Do something predictable for an UNPREDICTABLE branch. | Ali Saidi | |
| 2010-11-11 | Params: Fix an off by one error and a misleading comment. | Gabe Black | |
| 2010-11-11 | SimObject: Add a comment near clear_child that it's unlikely to be called. | Gabe Black | |
| 2010-11-11 | SPARC: Clean up some historical style issues. | Gabe Black | |
| 2010-11-10 | Update EIO regressions for last set of patches | Ali Saidi | |
| 2010-11-09 | scons: Work around for old versions of scons mistaking strings for sequences. | Gabe Black | |
| 2010-11-09 | SimObject: Use "self" when calling the clear_child method. | Gabe Black | |
| 2010-11-08 | X86: Fix X86_FS compilation. | Gabe Black | |
| 2010-11-08 | ARM: Update SE stats for TLB stats additions | Ali Saidi | |
| 2010-11-08 | ARM: Add full-system regressions | Ali Saidi | |
| 2010-11-08 | ARM: Add some TLB statistics for ARM | Ali Saidi | |
| 2010-11-08 | ARM: Add checkpointing support | Ali Saidi | |
| 2010-11-08 | ARM: Add support for M5 ops in the ARM ISA | Ali Saidi | |
| 2010-11-08 | ARM: Keep the warnings to a minimum. | Ali Saidi | |
| These warnings still need to be addresses, but pages of them is counterproductive. | |||
| 2010-11-08 | Mem: Finish half-baked support for mmaping file in physmem. | Ali Saidi | |
| Physmem has a parameter to be able to mem map a file, however it isn't actually used. This changeset utilizes the parameter so a file can be mmapped. | |||
| 2010-11-08 | Bus: Have the I/O devices that return address ranges print them out. | Ali Saidi | |
| This way we actually get device names associated with the devices. | |||
| 2010-11-08 | ARM: Don't return the result of a table walk the same cycle it's completed. | Ali Saidi | |
| The L1 cache may have been accessed to provide this data, which confuses it, if it ends up being accesses twice in one cycle. Instead wait 1 tick which will force the timing simple CPU to forward to its next clock cycle when the translation completes. Also prevent multiple outstanding table walks from occuring at once. | |||
| 2010-11-08 | scons: add a parameter to configure SCons' build cache | Ali Saidi | |
| 2010-11-08 | ARM/Alpha/Cpu: Stats change for prefetchs to be more like normal loads. | Ali Saidi | |
| 2010-11-08 | ARM/Alpha/Cpu: Change prefetchs to be more like normal loads. | Ali Saidi | |
| This change modifies the way prefetches work. They are now like normal loads that don't writeback a register. Previously prefetches were supposed to call prefetch() on the exection context, so they executed with execute() methods instead of initiateAcc() completeAcc(). The prefetch() methods for all the CPUs are blank, meaning that they get executed, but don't actually do anything. On Alpha dead cache copy code was removed and prefetches are now normal ops. They count as executed operations, but still don't do anything and IsMemRef is not longer set on them. On ARM IsDataPrefetch or IsInstructionPreftech is now set on all prefetch instructions. The timing simple CPU doesn't try to do anything special for prefetches now and they execute with the normal memory code path. | |||
| 2010-11-08 | ARM: Make all ARM uops delayed commit. | Ali Saidi | |
| 2010-11-08 | sim: Use forward declarations for ports. | Ali Saidi | |
| Virtual ports need TLB data which means anything touching a file in the arch directory rebuilds any file that includes system.hh which in everything. | |||
 |
index : gem5 | |
| gem5 |
| summaryrefslogtreecommitdiff |