summaryrefslogtreecommitdiff
AgeCommit message (Collapse)Author
2019-03-21ext,tests: Add back failing exceptionsJason Lowe-Power
Change-Id: Idf4ba8a2a3888787abf33d1a4ac52fcf146ce732 Signed-off-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17452 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
2019-03-21tests,ext: Add skip_cleanup implementation for TempdirFixtureJason Lowe-Power
Change-Id: Idc5ec9309a4ef3c0ad0c7e8b2df47294acc97ec4 Signed-off-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17451 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
2019-03-21ext,tests: Make return code based on test resultsJason Lowe-Power
This patch also fixes a spelling mistake. Change-Id: I8635216e512c10913a9cda54541d7e31e0d22a40 Signed-off-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17450 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
2019-03-21ext,test: Provide default terminal sizeJason Lowe-Power
When creating the separator for printing things to the terminal (=.*) we use an ioctl that isn't supported in some sandboxed environments. When running on the Google jenkins server (kokoro) it errors with an IOError. Change-Id: I148dd87cffe6e93d6723a386aecf9a9ea6c5b455 Signed-off-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17449 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2019-03-21cpu-kvm: Added informative error messageRyan Gambord
PerfKvmCounter::attach fails if the user doesn't have privileges to make the perf_event_open syscall. This is the default privilege setting since kernel 4.6. I've seen some users in the mailing list resort to running as root; changing the perf_event_paranoid setting is an alternative. Change-Id: I2bc6f76abb6e97bf34b408a611f64b1910f50a43 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17508 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2019-03-20mem-cache: Added the STeMS prefetcherJavier Bueno
Reference: Stephen Somogyi, Thomas F. Wenisch, Anastasia Ailamaki, and Babak Falsafi. 2009. Spatio-temporal memory streaming. In Proceedings of the 36th annual international symposium on Computer architecture (ISCA '09). ACM, New York, NY, USA, 69-80. Change-Id: I58cea1a7faa9391f8aa4469eb4973feabd31097a Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/16423 Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2019-03-19systemc: Hook up gem5_getPort to the gem5 getPort mechanism.Gabe Black
Change-Id: I771607c4436f4c1ca9d355d1da52924308cfc3b3 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17229 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Gabe Black <gabeblack@google.com>
2019-03-19arch, cpu, dev, gpu, mem, sim, python: start using getPort.Gabe Black
Replace the getMasterPort, getSlavePort, and getEthPort functions with getPort, and remove extraneous mechanisms that are no longer necessary. Change-Id: Iab7e3c02d2f3a0cf33e7e824e18c28646b5bc318 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17040 Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2019-03-19python: Switch to the new getPort mechanism to connect ports.Gabe Black
This retrieves ports using the getPort method, and connects them using the bind method on the ports themselves. Any smarts as far as what type of peers are allowed to connect or how they connect is left up to the individual bind methods. Change-Id: Ic640d1fce8af1bed411116e5830edc4a8a0f9d66 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17039 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2019-03-19mem: Move bind() and unbind() into the Port class.Gabe Black
These are now pure virtual methods which more specialized port subclasses will need to implement. The SlavePort class implements them by ignoring them and then providing parallel functions for the MasterPort to call. The MasterPort's methods do basically what they did before, except now bind() uses dynamic cast to check if its peer is of the appropriate type and also to convert it into that type before connecting to it. Change-Id: I0948799bc954acaebf371e6b6612cee1d3023bc4 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17038 Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2019-03-19sim: Add a getPort function to SimObject.Gabe Black
This will retrieve a Port object from a given SimObject (which might not be a MemObject) no matter what flavor of Port it is. Change-Id: I636b85e9d4929a05a769e165849106bcb5f3e9c1 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17037 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2019-03-19util: Build m5 with -no-pie flagRyan Gambord
Added -no-pie flag to link /util/m5 to support newer versions of GCC that enable PIE by default. Tested for backwards compatibility with GCC 4.3, which, only warns for the unrecognized flag. Change-Id: I4b6df593936346b9d3e2fe29a5d85dde78b7cc5e Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17429 Reviewed-by: Gabe Black <gabeblack@google.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2019-03-18python: Change || to && for MessageBuffers in connectPorts.Gabe Black
The connectPorts function currently checks if *either* of the peers in a port connection are a MessageBuffer, and if so will ignore the connection. This CL changes that || into a && so that *both* of the peers need to be a Ruby types (either a MessageBuffer or Network) for the connection to be ignored. That makes it easier to contain that abnormal behavior to those types instead of having it apply even when other types of port owners are involved. Unfortunately the number of interesting Ruby types is unbounded, but these are the types with ports as of today. This mechanism will hopefully be replacedall together so this should be a temporary issue. Change-Id: I140498770e5d37eb2abd3d99261d47e111f1c8ab Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17031 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2019-03-18python: Improve how templated SimObject classes are handled.Gabe Black
When setting up a SimObject's Param structure, gem5 will autogenerate a header file which attempts to declare the SimObject's C++ type. It has had at least some level of sophistication there where it would pull off the namespaces ahead of the class name and handle them properly, but it didn't know how to handle templates. This change improves that handling in two ways. First, it adds a new magical SimObject attribute called 'cxx_template_params' which is used to specify what the template parameters are as a list. For instance, if your SimObject was a template which took an integer constant as its first parameter and a type as its second, this attribute could look like the following: cxx_template_params = [ 'int FOO', 'class Bar' ] Importantly, if there are any default values for these template parameters, they should *not* be included here, they should be specified where the class is later defined. The second new mechanism is to add an internal CxxClass in the SimObject.cxx_param_decl method. This class accepts the class signature in the cxx_class attribute and the cxx_template_params and does two things. First, it strips off namespaces like in the old implementation. Second, it extracts and processes any template arguments attached to the class. If these are constants (as determined by the contents of cxx_template_params), then they are stored verbatim. If they're types, then they're recursively expanded into a CxxClass and stored that way. Note that these are the *values* of the template arguments, where as cxx_template_params lists the *types* and *names* of those arguments. In our earlier example, if cxx_class was: cxx_class = 'CoolClasses::ClassName<12, Fruit::Apple>' Then CxxClass would extract the namespace 'CoolClasses', the class name 'ClassName', the argument '12', and the argument 'Fruit::Apple'. That second argument would be expanded into a CxxClass with the namespace 'Fruit' and the class name 'Apple'. Importantly here, because there were no default arguments given in cxx_template_params, all "hidden" arguments which would fall through to their defaults need to be fully specified in cxx_class. The CxxClass has a method called declare() which uses the information extracted earlier to output all of the "stuff" necessary for declaring the given class, including opening any containing namespaces and putting template<...> ahead of the actual class declaration with the template parameters specified. If any of the template arguments are themselves CxxClass instances, then they'll be recursively declared immediately before the current class is. An alternative solution to this problem might be to include the header file which actually defines the cxx_class type to avoid having to come up with a declaration. Unfortunately this doesn't work since it can set up include loops where the SimObject C++ header file includes the param header to get access to the Param type, but that includes the C++ header to get access to the SimObject type. This also makes it harder for SimObjects to refer to each other, since they rely on the declaration in the params header files when declaring a member pointer to that type in their own Param structures. Change-Id: I68cfc36ddff6d789eb4cdef5178c4619ac2cc8b1 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17228 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Gabe Black <gabeblack@google.com>
2019-03-18scons: fix disable_partial logic for fast binaryHoa Nguyen
Partial linking should be disabled on darwin; however, the script fails to do so when force_lto is set, which results in gem5 building with fast option fails on macOS. This fix changes disable_partial logic, which should be True once it's True. Signed-off-by: Hoa Nguyen <hoanguyen@ucdavis.edu> Change-Id: I77d2a4cc4a9bf5c92c800c004eb744bb7081c42e Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/16888 Reviewed-by: Gabe Black <gabeblack@google.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2019-03-18util: changed shebang on gem5img.py to python2.7Ryan Gambord
Change-Id: Id1a2112ce940bf6721609e2637d925d35e5ded8a Signed-off-by: Ryan Gambord <gambordr@oregonstate.edu> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17408 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2019-03-18mem-cache: tautological comparison of byteOrderAndrea Mondelli
Error: build/X86/mem/cache/prefetch/indirect_memory.cc:56:24: error: result of comparison of constant -1 with expression of type 'const ByteOrder' is always false [-Werror,-Wtautological-constant-out-of-range-compare] fatal_if(byteOrder == -1, "This prefetcher requires a defined ISA\n"); ~~~~~~~~~ ^ ~~ build/X86/base/logging.hh:205:14: note: expanded from macro 'fatal_if' if ((cond)) { \ ^~~~ 1 error generated. Fix: cast of constant (-1) used in comparison Change-Id: I3deb154c2fe5b92c4ddf499176cb185c4ec7cf64 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17388 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2019-03-18configs: Use absolute import pathsAndreas Sandberg
Use absoluate import paths to be Python 3 compatible. This also imports absolute_import from __future__ to ensure that Python 2.7 behaves the same way as Python 3. Change-Id: Ica06ed95814e9cd3e768b3e1785075e36f6e56d0 Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/16708 Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
2019-03-15mem: Removed circular include refRyan Gambord
If BasicLink.hh is modified, the style checker forces a reordering of the includes, which results in build errors because it ends up including Topology.hh before including its xxxParams.hh files, which include forward declarations of the BasicLink family of classes, and so Topology.hh throws errors that BasicLink etc. are not declared. Change-Id: I664a0652e53f0cc61763c2190a980c655b85d397 Signed-off-by: Ryan Gambord <gambordr@oregonstate.edu> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17270 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2019-03-15mem-cache: Added the Indirect Memory PrefetcherJavier Bueno
Reference: Xiangyao Yu, Christopher J. Hughes, Nadathur Satish, and Srinivas Devadas. 2015. IMP: indirect memory prefetcher. In Proceedings of the 48th International Symposium on Microarchitecture (MICRO-48). ACM, New York, NY, USA, 178-190. DOI: https://doi.org/10.1145/2830772.2830807 Change-Id: I52790f69c13ec55b8c1c8b9396ef9a1fb1be9797 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/16223 Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2019-03-15mem: Move the Port base class into sim.Gabe Black
The Port class is going to be officially used for more than just memory system connections. Change-Id: I493e721f99051865c5f0c06946a2303ff723c2af Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17036 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2019-03-15dev: Make EtherInt inherit from Port.Gabe Black
This way a common function can return EtherInt (and master and slave ports). Change-Id: I1215baaad918ef0352b228877241b2b6dd2503fc Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17035 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Gabe Black <gabeblack@google.com>
2019-03-15mem: Track the MemObject owner in MasterPort and SlavePort.Gabe Black
These types are much more tied to MemObjects and the gem5 memory protocol than the Port or BaseMasterPort and BaseSlavePort classes. Change-Id: I36bc8c75b9c74d28ee8b65dbcbf742cd41135742 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17032 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Gabe Black <gabeblack@google.com>
2019-03-15python: Simplify connectPorts() around EtherObject/EtherDevice.Gabe Black
EtherDevice now inherits EtherObject and shares the same getEthPort virtual function, so there's no need to treat them separately any more. Change-Id: Ia6c147fd97fece4a281c296521a7b095f793d32e Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17030 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2019-03-15dev: Make the EtherDevice class inherit EtherObject.Gabe Black
This avoids having to define two parallel versions of the getEthPort function, and the complex dynamic_cast macrame in connectPorts(). Change-Id: I24c09864005ff39a049e50d7245ff17e9480edea Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17029 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2019-03-15dev: Turn EtherObject into an interface class.Gabe Black
This class used to drive from SimObject so that it could be derived from to get both the interface and SimObject while still using single inheritance. With this change, EtherObject is now just an interface class with only one pure virtual function which can be inherited alongside SimObject. This makes it more flexible so that it can be used in places where you might want a different inheritance hierarchy, for instance to inherit from MemObject. Change-Id: I0f07664d104eed012cf4ce6e30c416ada19505a7 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17028 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2019-03-15mem-cache: Fix write hit latency calculation orderDaniel
Patch 6d8694a5fb5cfb905186249581cc6a3fde6cc38a changes the order at which the access latency is calculated for hits. This order is incorrect, since the calculations must use the blk's whenReady value before the access is satisfied. Change-Id: I30dae5435f54200cc8fdf71fd0dbd2cf9c6f8b17 Signed-off-by: Daniel <odanrc@yahoo.com.br> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17190 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2019-03-14python: Teach cxxMethod how to set return_value_policy.Gabe Black
This is passed through to the underlying call to PyBindMethod. Change-Id: Ib46c55664ba0707464bb84e137a0fad817aea1bb Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17034 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2019-03-14python: Teach PyBindMethod how to set return_value_policy.Gabe Black
Change-Id: Ia208e43672672556b36f905e8f71dce44b978d22 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17033 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2019-03-14cpu: Refactor of Physical Register implementationAndrea Mondelli
The implementation of the PhyRegId class is shared between multiple cpu models. The o3/misc.hh should only be included in o3 models. This patch removes the dependencies between different model implementations, allowing to add new O3-like CPU model. Change-Id: Ibb812517043befe75c48fab3ce9605a0d272870b Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/16908 Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com> Reviewed-by: Bradley Wang <radwang@ucdavis.edu> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2019-03-14python: Fix unknown params and proxy multiplicationDaniel R. Carvalho
One of the recent changes made params not visible anymore: NameError: global name 'params' is not defined This is fixed by adding the proper import statement. However, the second error makes the multiplication values be assigned to other proxies (that are not even used on the multiplication). A workaround is added to prevent this from happening by extending "*=". Change-Id: I3ad276a456efff62058672d16caac2b3ad1b326b Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17048 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2019-03-14dev-arm: cleanup of gicv3 CPU interface code and fixesJairo Balart
Change-Id: I4643140f60da4dc9179b5bfed1e3ddd7c2f23091 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/16484 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
2019-03-14arch-arm,cpu: Add initial support for Arm SVEGiacomo Gabrielli
This changeset adds initial support for the Arm Scalable Vector Extension (SVE) by implementing: - support for most data-processing instructions (no loads/stores yet); - basic system-level support. Additional authors: - Javier Setoain <javier.setoain@arm.com> - Gabor Dozsa <gabor.dozsa@arm.com> - Giacomo Travaglini <giacomo.travaglini@arm.com> Thanks to Pau Cabre for his contribution of bugfixes. Change-Id: I1808b5ff55b401777eeb9b99c9a1129e0d527709 Signed-off-by: Giacomo Gabrielli <giacomo.gabrielli@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/13515 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2019-03-12scons: Don't use isdir in AddLocalRPATH.Gabe Black
isdir isn't a nice way to check if an FS.Base is a File or a Dir as was initially assumed, it literally checks if a path can be stat-ed and is reported as a directory by stat. This means that if a directory is going to be created as part of the build, the result of that test will change depending on whether that part of the build has happened successfully before. A better check which behaves as originally intended is to check whether the Node is an instance of the SCons.Node.FS.Dir class. Change-Id: Id041917d50b768a8205769c0a05320f92b09993c Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17128 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Gabe Black <gabeblack@google.com>
2019-03-12sim: Add size to array unserialization error messageDaniel R. Carvalho
Add both acquired and expected size information to array unserialization error message. Change-Id: Ic0a493c5a7860066eb992e9e91e7a4746b197579 Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/16542 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2019-03-12dev-arm: cleanup of gicv3 codeJairo Balart
Change-Id: I9aba90022f6408838c4ab87c6b90bba438752e53 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/16222 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
2019-03-12mem-cache: Removed default arg from get() in prefetch/base.hhRyan Gambord
commit b0d1643 caused building against NULL to break due to NULLIsa::GuestByteOrder not being defined. Removal of default argument in src/mem/cache/prefetch/base.hh fixes this. Change-Id: I99a4abb4be1418fadec145481164f7caa3334ca0 Signed-off-by: Ryan Gambord Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17070 Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2019-03-11arch-hsail: changed gen.py shebang from python(3) to python2.7Ryan Gambord
gen.py includes code_formatter from m5.util. code_formatter uses the python2 __metaclass__ attribute, which is ignored by python3, causing the code_formatter.pattern attribute to be unset. This prevented scons from building against HSAIL_X86 Signed-off-by: Ryan Gambord <gambordr@oregonstate.edu> Change-Id: I5a8bf9e730fd629eb7f9a7ac2dce928235a0dae4 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17008 Reviewed-by: Andrea Mondelli <Andrea.Mondelli@ucf.edu> Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com> Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>
2019-03-11arch-arm: Fixing implicit fallthrough build errorsRyan Gambord
2c242d6 introduced implicit-fallthrough errors when building against ARM. Added "default: return new Unknown(machInst);" to offending switch statements; please verify this is the corret behavior Signed-off-by: Ryan Gambord Change-Id: I5f5e3661ec562d4a3b2699e07d1195e6877ff959 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17071 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
2019-03-11mem-cache: Revert "mem-cache: Remove Packet dependency in Tags"Daniel R. Carvalho
Reverting patch due to polymorphism limitations. This reverts commit 86a54d91936b524c0ef0f282959f0fc29bafe7eb. Change-Id: Ie032dcc5176448c62118c89732b3cc6b8efd5a13 Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17049 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2019-03-10mem-cache: Added extra information to PrefetchInfoJavier Bueno
Added additional information to the PrefetchInfo data structure - Whether the event is triggered by a cache miss - Whether the event is a write or a read - Size of the data accessed - Data accessed by the request Change-Id: I070f3ffe837ea960a357388e7f2b8a61d7b2196c Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/16583 Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2019-03-07mem-cache: Add header delay to handleFill whenReadyDaniel R. Carvalho
A prefetch response will have a header delay, which was not being taken into account. Change-Id: I66a071bc81ef41b8c0de37aa2df75171d1979a6f Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/14895 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2019-03-07mem-cache: Allow tag-only accesses on latency calculationDaniel R. Carvalho
Some accesses only need to search for a tag in the tag array, with no need to touch the data array. This is the case for CleanEvicts, evicts that don't find a corresponding block entry (since a write cannot be done in parallel with tag lookup), and maintenance operations. Change-Id: I7365a915500b5d7ab636d49a9acc627072a7f58e Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/14878 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2019-03-07mem-cache: Add lookup latency to access' whenReadyDaniel R. Carvalho
When dealing with writebacks, as soon as the packet metadata arrives there will be a tag lookup, done sequentially because a write can't be done in parallel. While the tag lookup is being done, the payload will arrive. When both the payload are present and the tag is correct block entry is determined the fill happens. Change-Id: If1a0085d742458b675bfc012b6d908d9d9a25e32 Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/14877 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2019-03-07mem-cache: Fix recvTimingReq doWritebacks tickDaniel R. Carvalho
Before being sent to the writebuffer, the evicted blocks must be selected for replacement, and therefore the access latency must be applied. The forward latency is then applied on top of that delay. Change-Id: I16a25a8bf6051f63eb7a02fe66acb6af26d434fc Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/14736 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2019-03-07mem-cache: Use header delay on latency calculationDaniel R. Carvalho
Previously the bus delay was being ignored for the access latency calculation, and then applied on top of the access latency. This patch fixes the order, as first the packet must arrive before the access starts. Change-Id: I6d55299a911d54625c147814dd423bfc63ef1b65 Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/14876 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2019-03-07mem-cache: Remove old todo about latency in hit functionDaniel R. Carvalho
The header and payload delay have already been accounted and zeroed previous to calling this function. The probe is not allowed to modify the packet, therefore no extra delays are added, and it is safe to remove the todo note. Change-Id: I8ddf7e189fbe609cdec34364f3c013427930daf7 Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/14875 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2019-03-01util, tlm: Fix a memory error in the SCMasterPort class.Gabe Black
In the b_transport method of the SCMasterPort class, there is a check which determines whether the packet being sent to gem5 should be deleted once the call to sendAtomic returns. This was deleting the packet if extension was *not* nullptr. This check should delete the packet if the extension *is* nullptr. The reasoning is that the extension will equal nullptr if there was no gem5 packet in an extension and a new one needed to be allocated. If there was an extension, ie if extension is not nullptr, then that's where the packet came from which therefore doesn't belong to us. In that case, we need to leave it alone and let its owner clean it up. With the check reversed, this method will either leak allocated packets it should delete, or delete packets it shouldn't that someone else will likely try to use later. Change-Id: I61578d910be6e5085b9fc0ddaa82468b1ac68578 Reviewed-on: https://gem5-review.googlesource.com/c/16949 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Gabe Black <gabeblack@google.com>
2019-03-01tlm: Add some includes to some tlm_utils header files.Gabe Black
These bring in some pieces that those headers use but were only coincidentally included by something else when they were used. Change-Id: I5f119260d8f25d914d8545a60834f23f65f82d0c Reviewed-on: https://gem5-review.googlesource.com/c/16948 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Gabe Black <gabeblack@google.com>
2019-03-01python: Fix issue when Self proxy resolves to a another proxyAndreas Sandberg
The problem occurs when a proxy is being resolved to another proxy that hasn't been resolved yet. The problematic case that was triggering this issues in the VGIC. It was caused by parameters looking a bit like this: gic = Param.GicV2(Parent.any) some_param = Param.Int(Self.gic.some_param) When 'some_param' was resolved, it found the 'gic' parameter in Self. However, that parameter hadn't been resolved yet, so the existing code was setting the proxy evaluation context to the unresolved Parent.any proxy without first unproxying it. It seems like this bug depends on the graph traversal order and I have so far only seen it when compiling gem5 with Python 3. Change-Id: Iea12cc138765e70bfd6bb776b1efa012364db066 Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/16004 Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-07-04 08:57:19 +0000